This page details my EE 563 VLSI design project, a 24-Bit PRN Code Generator. The design was implemented in 2.0-micron SCNA CMOS technology, fabricated by MOSIS. The contents of this page are based primarily on my project report. Currently, the various appendices (including, primarily, the Spice simulation results, and some figures that were created externally) are not readily available.
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