/* * ============================================================================ * CP_1610: CP-1610 internal status structures and functions * * Author: J. Zbiciak * Last Revision: 9/5/98 * ============================================================================ * * ============================================================================ */ #ifndef _CP_1610_H #define _CP_1610_H /* * ============================================================================ * CPU_T -- CP-1610 internal state structure * CPU_P -- pointer to CPU object * CPU_WORD_T -- Tpye for holding CPU words. * CPU_MEMR_T -- Memory/peripheral accessor functions * CPU_MEMW_T -- Memory/peripheral accessor functions * * This structure contains all the state information related to an instance * of a CP-1610 processor. This includes the state of the register file, * current cycle count, and pointers to the memory subsystem and peripherals. * * Memory mapped peripherals are invoked from the CPU via the rd_mem and * wr_mem arrays. The CP-1610 object "decodes" addresses to the granularity * specified by CPU_DECODE_PAGE. Based on this decoding, the function * pointer specified in the rd_mem[] or wr_mem[] array is called to perform * the specified access. Note that the return value from wr_mem is ignored. * * If finer granularity than CPU_DECODE_PAGE is desired, either make * CPU_DECODE_PAGE smaller, or register a "decoder" function instead which * performs the finer-granularity decoding. * * The memory read functions in rd_mem[] are declared like so: * * cpu_word_t -- return data (if this is a read) * mem_rd_function * ( * cpu_p cpu, -- pointer to associated CPU * int * wait, -- wait-states incurred (if any) * cpu_word_t addr -- address being accessed * ); * * The memory write functions in wr_mem[] are declared like so: * * void * mem_wr_function * ( * cpu_p cpu, -- pointer to associated CPU * int * wait, -- wait-states incurred (if any) * cpu_word_t addr, -- address being accessed * cpu_word_t data -- data being written * ); * * Simple RAM/ROM memory objects are declared in this file. Peripheral * accessor objects are defined separately. * * Since the CPU tries to cache decoded instructions, the CPU state * structure also includes "cacheable" bits for each of the pages. If a * page is not marked "cacheable", then no instruction spanning that page * is allowed to be "cached". The page size for the cacheability bits is * identical to the decoding page size. NOTE: The current code assumes * that the C type "unsigned" is at least 32 bits. It stores the cacheable * bits as a bit-vector. * ============================================================================ */ #define CPU_MEMSIZE (16) /* Address size in bits */ #ifndef CPU_DECODE_PAGE #define CPU_DECODE_PAGE (4) /* Granularity of address decode (bits) */ #endif typedef unsigned short cpu_word_t; typedef struct cpu_t *cpu_p; typedef struct instr_t *instr_p; typedef const struct instr_t *instr_kp; typedef int (*instr_func_t) (instr_p, cpu_p); typedef int (*instr_kfunc_t) (instr_kp, cpu_p); typedef cpu_word_t (*cpu_memr_t) (cpu_p, int *, cpu_word_t); typedef void (*cpu_memw_t) (cpu_p, int *, cpu_word_t, cpu_word_t); typedef struct cpu_t { #ifdef _TMS320C6X unsigned long tot_cycle; /* Elapsed cycle count */ unsigned long tot_instr; /* Total instructions executed */ #else unsigned long long tot_cycle; /* Elapsed cycle count */ unsigned long long tot_instr; /* Total instructions executed */ #endif cpu_word_t *raw_mem; /* Pointer to raw memory */ cpu_word_t r[8]; /* CPU registers */ cpu_word_t ext; /* EXT[0-3] pin state */ cpu_word_t int_vec; /* Interrupt vector. */ int S,C,O,Z,I,D; /* status bits. */ int intr; /* Current instr is interruptible */ int irq; /* Somebody wants an interrupt. */ cpu_memr_t rd_mem [1 << (CPU_MEMSIZE - CPU_DECODE_PAGE)]; cpu_memw_t wr_mem [1 << (CPU_MEMSIZE - CPU_DECODE_PAGE)]; unsigned cacheable [1 << (CPU_MEMSIZE - CPU_DECODE_PAGE - 5)]; instr_func_t execute [1 << CPU_MEMSIZE]; /* Decoded instructions */ instr_p instr [1 << CPU_MEMSIZE]; /* Decoded instructions */ #ifdef DEBUG_DECODE_CACHE int decoded [1 << CPU_MEMSIZE]; #endif int tot_cache; int tot_noncache; } cpu_t; #define CPU_RD(c,w,a) (c->rd_mem[(a)>>CPU_DECODE_PAGE]((c),(w),(a))) #define CPU_WR(c,w,a,d) (c->wr_mem[(a)>>CPU_DECODE_PAGE]((c),(w),(a),(d))) /* * ============================================================================ * CPU_INIT -- Initializes a CPU_T structure * * Currently, this sets up the CPU structure w/ 64K of 16-bit RAM. This * is not ideal and will be changed later. * ============================================================================ */ int cpu_init ( cpu_t *cpu ); /* * ============================================================================ * CPU_RUN -- Runs the CPU for some number of microcycles * * This is the main CPU loop. It is responsible for fetching instructions, * decoding them if necessary (or using predecoded instructions if possible) * and calling the required execute functions. * * The cpu_run function will run as many instructions as are necessary to * just barely exceed the specified number of microcycles. eg. It will * execute a new instruction if the specified total number of microcycles * has not yet been exceeded. The new instruction may exceed the specified * number of microcycles. The total number of microcycles exhausted is * returned as an int. * ============================================================================ */ int cpu_run ( cpu_t *cpu, unsigned microcycles ); /* * ============================================================================ * CPU_RD_MEM_8 -- Reads from an 8-bit memory. 0 wait states * CPU_RD_MEM_10 -- Reads from a 10-bit memory. 0 wait states * CPU_RD_MEM_12 -- Reads from a 10-bit memory. 0 wait states * CPU_RD_MEM_14 -- Reads from a 10-bit memory. 0 wait states * CPU_RD_MEM_16 -- Reads from a 16-bit memory. 0 wait states * CPU_RR_NULL -- Ignored read. 0 wait states * CPU_WR_MEM_8 -- Writes to an 8-bit memory. 0 wait states * CPU_WR_MEM_10 -- Writes to a 10-bit memory. 0 wait states * CPU_WR_MEM_12 -- Writes to a 12-bit memory. 0 wait states * CPU_WR_MEM_14 -- Writes to a 14-bit memory. 0 wait states * CPU_WR_MEM_16 -- Writes to a 16-bit memory. 0 wait states * CPU_WR_NULL -- Ignored write. 0 wait states * ============================================================================ */ cpu_word_t cpu_rd_mem_8 (cpu_p,int*,cpu_word_t); cpu_word_t cpu_rd_mem_10 (cpu_p,int*,cpu_word_t); cpu_word_t cpu_rd_mem_12 (cpu_p,int*,cpu_word_t); cpu_word_t cpu_rd_mem_14 (cpu_p,int*,cpu_word_t); cpu_word_t cpu_rd_mem_16 (cpu_p,int*,cpu_word_t); cpu_word_t cpu_rd_null (cpu_p,int*,cpu_word_t); void cpu_wr_mem_8 (cpu_p,int*,cpu_word_t,cpu_word_t); void cpu_wr_mem_10 (cpu_p,int*,cpu_word_t,cpu_word_t); void cpu_wr_mem_12 (cpu_p,int*,cpu_word_t,cpu_word_t); void cpu_wr_mem_14 (cpu_p,int*,cpu_word_t,cpu_word_t); void cpu_wr_mem_16 (cpu_p,int*,cpu_word_t,cpu_word_t); void cpu_wr_null (cpu_p,int*,cpu_word_t,cpu_word_t); /* * ============================================================================ * CPU_ADD_RAM -- Adds a RAM starting at a given address of a given size * CPU_ADD_ROM -- Adds a ROM starting at a given address of a given size * ============================================================================ */ int cpu_add_ram ( cpu_t *cpu, int width, cpu_word_t addr, cpu_word_t size, int cache ); int cpu_add_rom ( cpu_t *cpu, int width, cpu_word_t addr, cpu_word_t size, int cache, const cpu_word_t *image ); #endif /* * ============================================================================ * Copyright (c) 1998, Joseph Zbiciak. * ============================================================================ */