旼컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴커 � Mattel Electronics Intellivision � � Intelligent Television � 읕컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴켸 栢 � "Mattel Electronics Presents" 栢栢栢 � 栢� � 栢栢� 旼컴컴컴컴컴컴컴컴컴� 栢 쿏e Re Intellivision� 읕컴컴컴컴컴컴컴컴컴� 栢 栢栢栢 (In Latin "All About Intellivision") 栢栢栢 � � 栢 � Compilation By William M. Moeller 栢 � 栢 � 컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴 Last Modified November 8, 1997 컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� Chapter IX "Intellivision T-Card" 컴컴컴컴컴컴컴컴컴컴 Nov 08/97 - Revision 0.0 - Print in condensed mode If you have any suspicions of errors or questions, ask now while we have the cart to check. It will be returned to its owner soon. 컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� INTELLIVISION EDGE CONNECTOR Motherboard CART ROM TOP BOTTOM # # ?? NC ?? - 2 1-GND -b22 STIC Pin 19 NC ?? - 4 3--MSYNC -b21 Matl Pin 7 NC ?? - 6 5-D7 -b20 STIC Pin 9 GND ?? - 8 7-D8 -b19 STIC Pin 15* GND ?? -10 9-D6 -b18 Supply ?? GND ?? -12 11-D9 -b17 CPU INTRM NC INT -14 13-D5 -b16 GND -16 커M 15-D10 -b15 GND -18 캑T 17-D4 -b14 GND -20 캑H 19-D11 -b13 GND -22 캑R 21-D3 -b12 GND -24 캑B 23-D12 -b11 GND -26 캑R 25-D13 -b10 GND -28 켸D 27-D2 -b9 CPU BUSAK NC ?? -30 29-D14 -b8 旼STIC BC1 컴컴 旼컴 *1 -32 31-D1 -b7 � STIC BC2 컴컴 C넬컴 *2 -34 33-D0 -b6 � STIC BDIR 컴컴 A납旼 *3 -36 SLOT 35-D15 -b5 � Mattel Pin 10 R납읕 *3 -38 컴컴�37-*3 -b4 � Mattel Pin 12 T냅컴 *2 -40 컴컴-39-*2 -b3 쳐Mattel Pin 14 읕컴 *1 -42 컴컴�41-*1 -b2 � GND GND GND-44 43-VCC -b1 � 읕Timing Read/Write etc. 旼컴쩡컴쩡컴컫컴컴컴쩡컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� 쿍C1쿍C2쿍DIR� � � 쳐컴탠컴탠컴컵컴컴컴탠컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� � 0 � 0 � 0 쿙ACT � CPU inactive, and disconnected from bus � 쳐컴탠컴탠컴컵컴컴컴탠컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� � 0 � 0 � 1 쿍AR � A memory address is being presented on the BUS � 쳐컴탠컴탠컴컵컴컴컴탠컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� � 0 � 1 � 0 쿔AB � CPU is acknowledging an interrupt request � � � � � � External logic must place the starting address � � � � � � for the interrupt service routine on the bus. � 쳐컴탠컴탠컴컵컴컴컴탠컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� � 0 � 1 � 1 쿏WS � Data write strobe to memory. � 쳐컴탠컴탠컴컵컴컴컴탠컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� � 1 � 0 � 0 쿌DAR � This signal identifies a time interval during � � � � � � which the Data/Address bus is floated, while � � � � � � data input on the Data Bus is being interpreted � � � � � � as the effecitve memory address during a direct � � � � � � memory addressing operation. � 쳐컴탠컴탠컴컵컴컴컴탠컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� � 1 � 0 � 1 쿏W � Data is being written to memory. � � � � � � Preceeds DWS by one cycle. � 쳐컴탠컴탠컴컵컴컴컴탠컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� � 1 � 1 � 0 쿏TB � Read strobe (external device is to place data � � � � � � on the bus. � � 1 � 1 � 1 쿔NTAK � Interrupt acknnowledge. Followed by IAD. � 읕컴좔컴좔컴컨컴컴컴좔컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� � BAR MC1 � NACT MC2 � DTB MC3 � CP-1600 퀃1퀃2퀃3퀃4� � � � 퀃1퀃2퀃3퀃4� Instruction Fetch timing � � � � 퀃1퀃2퀃3퀃4� � � � � 컴컴컴컴컴컴컴컴컴컴컴컴 � � � � � � � � � � � � � 旼� 旼� 旼� 旼� 旼� 旼� 旼� 旼� O1 컴� 읕컴� 읕컴� 읕컴� 읕컴� 읕컴� 읕컴� 읕컴� 커| 旼�| 旼�| 旼� 旼�| 旼� 旼�| 旼� 읕컴� 읕컴� 읕컴� 읕컴� 읕컴� 읕컴� 읕컴� 읕컴 O2 | | | | 旼컴컴컴컴컴� 컴컴컴컴컴컴컴컴컴컴컴컴컴� 읕컴컴컴� BC1 | | | | 旼컴컴컴컴컴� 컴컴컴컴컴컴컴컴컴컴컴컴컴� 읕컴컴컴� BC2 旼컴컴컴컴컴� 컴� | | 읕컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� BDIR | 旼컴컴컴컴� 旼컴� 컴컴훫xx� 쳐컴컴컴컴컴캑 쳐컴컴컴컴컴 Address 읕컴컴컴컴� 읕컴� Address out Data in TCART Theory of Operation 쳐컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� 컴컴컴컴컴컴컴컴컴컴컴컴컴� The TCART is designed to allow 4 independent banks of standard ROM or standard static RAM to be mapped into the 1610 address space. Each ROM bank can be up to 4K in size. Each static RAM bank can be up to 2K in size. Banks can be configured though DIP switches to start at any 4K address in the 1610's address space. The DIP switches also allow the selection of RAM/ROM, and in which portion of the 4K bank the 2K of RAM resides. TCART Construction � 컴컴컴컴컴컴컴컴컴켸 旼쩟쩟쩟쩟쩟쩟쩟쩟커 a 74LS374N high order data/address � 납납납납납납납납 � b 74LS374N low order data/address � � c 74LS42N 4 to 10 decoder � 旼� 旼� � d 74LS04N Hex inverter � � � � � 旼� � e 74LS08N Quad 2 input +NAND � 쿪� 쿫� � � � rhx ROM bank a (high) � � � � � 쿬� � rlx ROM bank a (high) � 읕� 읕� 읕� � J-M Toggle switches banks 1-4 � � n 54LS51J and-or-invert gate � 旼� 旼� � o 74LS00N quad 2 input +nand � 쿭� 쿮� � p 74LS05N 4 bit magnitude comparitor � � � � � � sn dip switches for base address ROM/RAM 旼컴컴컴컴컴컴컴켸 읕� 읕� 읕컴컴컴컴컴컴컴커 � � � tcart top view � � 旼컴컴컴커旼컴컴컴커旼컴컴컴커旼컴컴컴커 � � � rh1 납 rh2 납 rh3 납 rh4 � � � 읕컴컴컴켸읕컴컴컴켸읕컴컴컴켸읕컴컴컴켸 � � 旼컴컴컴커旼컴컴컴커旼컴컴컴커旼컴컴컴커 � � � rl1 납 rl2 납 rl3 납 rl4 � � � 읕컴컴컴켸읕컴컴컴켸읕컴컴컴켸읕컴컴컴켸 � � s1旼컴컴커 s2旼컴컴커 s3旼컴컴커 s4旼컴컴커 � � 읕컴컴켸 읕컴컴켸 읕컴컴켸 읕컴컴켸 � � 旼� 旼� 旼� 旼� � � 旼� 旼� � � 旼� 旼� � � 旼� 旼� � � 旼� 旼� � � � � 쿻� 쿽� 쿾� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 읕� 읕� 읕� 읕� 읕� 읕� 읕� 읕� 읕� 읕� 읕� 읕� � 읕컫컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴켸 읕컴컫컴컴컴좔컴컫컴컴컴좔컴컴쩡컴컴좔컴컴쩡컴컴� GLUE for GLUE for GLUE for GLUE for ROM/RAM ROM/RAM ROM/RAM ROM/RAM bank 1 bank 2 bank 3 bank 4 Standard 2732 EPROM's (4K) are used. The type of Static RAM used is such that the pinouts are identical to the 2732, with what would be A11 on the 2764, being used for R/W. What are now standard components need some support circuitry to connect them to the 1610 bus. The 1610 bus is muliplexed and carries both addresses and data. To connect RAM/ROM to the bus, essentially all that is needed are a couple of 8 bit latches to take and hold the address while it is presented to the address inputs on the RAM/ROM, some address decoding to select where the RAM/ROM resides, and some circuitry to decode the 1610 bus phases into something that can coordinate the data transfer. RAM/ROM is organized as 4 banks of 2 chips, each taking or returning 8 bits of the 16 bit value held at each memory address in the 1610's 64K address space. Address lines A0-A10 are connected in parallel to each RAM/ROM chip. The data ports of all chips taking/returning the high order data byte and all chips taking/returning the low order data byte byte are respectively connected in parallel. The Output Enable pin on each RAM/ROM chip (both banks) are connected together. For each of the four (high,low) banks the Chip -nable lines are tied to a common source, as is the A11 (ROM)- R/W (RAM) lines. Since the 1610 address bus is multiplexed, the address presented to RAM/ROM and the address decoding circuitry must first be latched to hold the value while data is read/written from RAM/ROM. The address latch consists of 2 74LS374 octal flip/flops that have their inputs tied directly to the 1610 data/address bus. Output control for these latches is constantly low. The address is latched on eather of the 1610's BAR or ADAR bus phases. Address bits (A0-A10) from the latches is presented directly to all RAM/ROM chips. A12-A15 is sent to the address decoding section associated with each of the 4 (high,low) RAM/ROM banks so that the appropirate Chip Enable signal is generated. A11 is routed through some logic that optionally replaces the signal with a Read/Write signal needed to support static RAM. Address decoding is accomplished through the use of a 74LS85N 4 bit comparitor. This chip compares 4 bits with 4 bits and returns the result. as A>B, A A=B is connected to a dip switch labeled ENA and allows the switch to enable/disable the A=B output of the comparator, thereby enabling/disabling the RAM/ROM bank. The MS4bits of the address presented through the latches (A12-A15) are presented to the A inputs of the comparitor, and 4 bits selected by DIP switches are presented to the B inputs of the comparitor. When the bits match, the A=B output is triggered (presuming it is enabled) indicating that the RAM/ROM bank should respond. For ROM use, the A=B signal could be directly used to generate the Chip Enable signal needed to select the Bank. However, to support RAM, the signal is modified so that the select signal is generated only when the address is in the upper half or lower half of the 4K window. (The static RAM used can be no more than 2K deep.) This selection is accomplished by looking at A11. RAM/ROM selection is accomplished by using the dip switches labeled RAM and RAMH. (RAM = RAM select, RAMH = RAM High Low select). When RAM is selcted, Chip Enable is asserted when A11 = RAMH. The RAM dip switch also used to select the signal sent to the A11(ROM),R/W(RAM) line on the RAM/ROM chip in its corresponding High/Low bank. When the dip switch RAM is in one position, A11 from the address latches is routed to A11 on the (presumed) ROM chips in the bank. In the alternate position a signal from the bus phase circuitry - indicating a bus write - is sent to the R/W line on the (presumed) RAM chips in the bank. The data output ports of the RAM/ROM chips are connected directly to the 1610's bus and do not require external latches or buffers. The RAM/ROM chips used must present or take their data to/from the 1610 bus only when the appropriate Chip Enable and Output Enable signals are given, and must keep their output ports in a high impedence state at all other times. Standard 27xx series EPROMS do this. At this point, I don't know what static RAM components are compatible. A rough conceptual sketch of the TCART is shown below. 16 bits of Data Returned/Taken 旼컴컴컴컴컴컴컴컴컴컴컴컴컴컴쩡컴컴컴컴컴쩡컴컴컴컴컴쩡컴컴컴컴컴� � � � � �  旼컴� A0-A10 旼좔� 旼좔� 旼좔� 旼좔� � � L 쳐컴컴컴컴컴�� R 쳐컴컴�� R 쳐컴컴�� R 쳐컴컴�� R � � Address � A � A12-A15 -OE� O � -OE� O � -OE� O � -OE� O � � Bus � T 쳐컴컴컴컴� �� M 쳐컴컴�� M 쳐컴컴�� M 쳐컴컴�� M � 컨컴컴컴쩡� C � A11 � � � 1 �� A11 � 2 �� A11 � 3 �� A11 � 4 �� A11 � � H 쳐컴컴컴� � � 읕컴� � R/W 읕컴� � R/W 읕컴� � R/W 읕컴� � R/W � 읕컴� � � � -CE � -CE � -CE � -CE � �  CLK 旼x훫켸 � � � � � � � � � � � � � 憫컴� � 憫컴� � 憫컴� � 憫컴� � � 旼좔� � � 읕�쿪 d쳐x컴컴쿪 d쳐x컴컴쿪 d쳐x컴컴쿪 d� � Address � � D 쳐컴컴� � 쿭 e� � 쿭 e� � 쿭 e� � 쿭 e� � Decoding BC1 � � E � � 퀁 c� � 퀁 c� � 퀁 c� � 퀁 c� � BC2 � � C � � 읕쩡描좔커 읕쩡描좔커 읕쩡描좔커 읕쩡描좔커 BDIR 읕� O � � A11 읕캑 G � 읕캑 G � 읕캑 G � 읕캑 G � � D � 읕컴컴컴컴� L 쳐컴컴�� L 쳐컴컴�� L 쳐컴컴�� L � � E 쳐컴컴컴컴컴컴컴컴� U 쳐컴컴�� U 쳐컴컴�� U 쳐컴컴�� U � 읕컴� R/W 읕컴� 읕컴� 읕컴� 읕컴� Note that each bank of RAM/ROM 1-4 consists of 2 chips, one holding the high order byte, and one holding the low order byte. 16 bits of data can be held at each address in the 1610 64K address space. Also note that for each bank of RAM/ROM there is separate address decoding and A11(R/W) and -CE signal generation. Each bank is independently configurable and may hold RAM or ROM starting at any 4K address. RAM may be configured to respond only to addresses only in the upper/lower half of the 4K window. Banks may be set to overlap, and while useless for use with ROM's, this allows an entire 4K address space to be filled with RAM. 2K from one bank, and 2K from another. Configurations can include... x = don't care. Any value/state. 旼컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� � TCART disabled. � 쳐컴컴컴컴쩡컴컴컴컫컴컴컴컴쩡컴컴컴컫컴컴컴컴� � � Bank 1 � Bank 2 � Bank 3 � Bank 4 � 쳐컴컴컴컴탠컴컴컴컵컴컴컴컴탠컴컴컴컵컴컴컴컴� � Ena � 0 � 0 � 0 � 0 � � RAM � x � x � x � x � � RAMH � x � x � x � x � � ADDRESS � x � x � x � x � 읕컴컴컴컴좔컴컴컴컨컴컴컴컴좔컴컴컴컨컴컴컴컴� 旼컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� � 8 K ROM installed at 05000H to 06FFFH � 쳐컴컴컴컴쩡컴컴컴컫컴컴컴컴쩡컴컴컴컫컴컴컴컴� � � Bank 1 � Bank 2 � Bank 3 � Bank 4 � 쳐컴컴컴컴탠컴컴컴컵컴컴컴컴탠컴컴컴컵컴컴컴컴� � Ena � 1 � 1 � 0 � 0 � � RAM � 0 � 0 � x � x � � RAMH � 0 � 0 � x � x � � ADDRESS � 5 � 6 � x � x � 읕컴컴컴컴좔컴컴컴컨컴컴컴컴좔컴컴컴컨컴컴컴컴� 旼컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� � 8 K ROM installed at 05000H to 06FFFH � � 2 K RAM installed at 0E000H to 0E7FFH � 쳐컴컴컴컴쩡컴컴컴컫컴컴컴컴쩡컴컴컴컫컴컴컴컴� � � Bank 1 � Bank 2 � Bank 3 � Bank 4 � 쳐컴컴컴컴탠컴컴컴컵컴컴컴컴탠컴컴컴컵컴컴컴컴� � Ena � 1 � 1 � 1 � 0 � � RAM � 0 � 0 � 1 � x � � RAMH � 0 � 0 � 0 � x � � ADDRESS � 5 � 6 � E � x � 읕컴컴컴컴좔컴컴컴컨컴컴컴컴좔컴컴컴컨컴컴컴컴� 旼컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� � 8 K ROM installed at 05000H to 06FFFH � � 4 K RAM installed at 0E000H to 0EFFFH � 쳐컴컴컴컴쩡컴컴컴컫컴컴컴컴쩡컴컴컴컫컴컴컴컴� � � Bank 1 � Bank 2 � Bank 3 � Bank 4 � 쳐컴컴컴컴탠컴컴컴컵컴컴컴컴탠컴컴컴컵컴컴컴컴� � Ena � 1 � 1 � 1 � 1 � � RAM � 0 � 0 � 1 � 1 � � RAMH � 0 � 0 � 0 � 1 � � ADDRESS � 5 � 6 � E � E � 읕컴컴컴컴좔컴컴컴컨컴컴컴컴좔컴컴컴컨컴컴컴컴� Tcart Circuit 쳐컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴� 컴컴컴컴컴컴컴� LS734 FUNCTION TABLE -------------------- Output CLK D Out CNTRL high order address/data low order address/data L ^ H H 74LS374N 74LS374N L ^ L L Octal D type Octal D type L L X QO Edge triggered Edge triggered H X X Z Flip/Flop Flip/Flop low on BAR or ADAR ? 旼컴컴컴컫컴컴컴컴컴컴컴컴컴컴컴컴컴커 4 -> 10 (output is inverted) � � 旼컴컴컴� � 旼컴컴컴� decoder 0000 -> 0111111111 � 읕퀰LK GND쳐 읕퀰LK GND쳐 74LS42N 0001 -> 1011111111 � (a12) o컴�5q 4q쳐o (a11) a4 캑5q 4q쳐 a3 旼컴컴컴� � b11-d4b캑5d 4d쳐 d3b-b13 b14-d4a캑5d 4d쳐 d3a-b12 nc 캑7 GND쳐 � b10-d5b캑6d 3d쳐 d2b-b15 b16-d5a캑6d 3d쳐 d2a-b9 nc 캑8 6쳐 nc 110 DWS � (a13) o컴�6q 3q쳐 a10 a5 캑6q 3q쳐 a2 nc 캑9 5쳐컴컴컴커 101 DW � (a14) o컴�7q 2q쳐 a9 a6 캑7q 2q쳐 a1 GND 캑d 4쳐컴컴커 � 100 BAR � b8-d6b캑7d 2d쳐 d1b-b17 b18-d6a캑7d 2d쳐 d1a-b7 bdir 캑c 3쳐컴커 � � 011 DTB � b5-d7b캑8d 1d쳐 d0b-b19 b20-d7a캑8d 1d쳐 d0a-b6 bc2 캑b 2쳐nc � � � 010 IAB � (a15) o컴�8q 1q쳐 a8 a7 캑8q 1q쳐 a0 bc1 캑a 1쳐커 � � � 001 ADAR � 캑+5 �-OC쳐 GND 캑+5 �-OC쳐 GND 캑+5 � 0첼 � � � � 000 NACT � 읕컴좔컴� 읕컴좔컴� 읕컴좔컴�o � � � � 읕컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴커 nc � � � � 74LS04N 74LS08N � � � � � 旼컴컴컴� 旼컴컴컴� � � � � � nc 캑4y GND쳐 nc 캑3y GND쳐 � � � � � GND 캑4a 3y쳐nc? GND 캑3b 2y쳐켸 bar � � � � a11 (c1ab) o컴컴컴컴캑5y 3a쳐GND GND 캑3a 2b쳐컴컴컴컴컴훫훫켸 � oa (bank 1) o컴컴컴컴캑5a 2y쳐o a11 (c3ab) nc 캑4y 2a쳐컴� � � � a11 (c2ab) o컴컴컴컴캑6y 2a쳐o oa (bank 3) GND 캑4b 1y쳐컴x컴� dtb � � � oa (bank 2) o컴컴컴컴캑6a 1y쳐o a11 (c4ab) GND 캑4a 1b쳐컴x컴x컴컴훫켸 � 캑+5 � 1a쳐o oa (bank 4) 캑+5 � 1a쳐컴좔훫컴컴켸 � 읕컴좔컴� 읕컴좔컴� � adar � hex QUAD a b y � � Inverter 2 input h h h � � y = -a + AND l x l � � x l l � � � � For the ROM chips below, -CE and A11 are generated for each � � High/Low chip set from the corresponding bank of address decoding � � RAM/ROM selection (glue) that follows. � � � � line goes low on BAR or DWS ? � � 旼컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴쩡컴컴컴컴컴컴컴컴컴컴컴컴컴� dw o � bank a � bank b � 旼컴컴컴컴컴컴컴컴컴커 � 旼컴컴컴컴컴컴컴컴컴커 � � 旼컴컴컴컴컴커 � � � 旼컴컴컴컴컴커 � � � 旼퀱3 c1h GND쳐 � � � 旼퀱3 c1l GND쳐 � � � 쳐퀱4 D2쳐� � � � 쳐퀱4 D2쳐� � 旼훫컴좔탠퀱5 D1쳐탠� 旼x컴좔탠퀱5 D1쳐탠� � � 쳐퀱6 D0쳐� � � 쳐퀱6 D0쳐� � � 읕퀱7 A0쳐� � � 읕퀱7 A0쳐� � � o캑-CE A1쳐� � � o캑-CE A1쳐� � � 旼캑A10 2732 A2쳐� � � 旼캑A10 2732 A2쳐� � 쳐컴x컴�-OE A3쳐탠쩡컴캑 � 쳐컴x컴�-OE A3쳐탠쩡컴� � � o훫컴퀮11 1 A4쳐� � � � � o훫컴퀮11 1 A4쳐� � � � � 旼탠캑A9 A5쳐� � � � � 旼탠캑A9 A5쳐� � � � � � 읕캑A8 A6쳐� � � � � � 읕캑A8 A6쳐� � � � � � 캑VCC 旼커 A7쳐� � � � � � 캑VCC 旼커 A7쳐� � � � � � 읕컴컨컴좔컴켸 � � � � � 읕컴컨컴좔컴켸 � � � � 읕컴컴컴컴컴컴컴컴컴컴� � � � 읕컴컴컴컴컴컴컴컴컴컴� � � � � � � � � � 旼컴컴컴컴컴컴컴컴컴커 � � � 旼컴컴컴컴컴컴컴컴컴커 � � � � 旼컴컴컴컴컴커 � � � � � 旼컴컴컴컴컴커 � � � � � 旼퀱3 c2h GND쳐 � � � � � 旼퀱3 c2l GND쳐 � � � � � 쳐퀱4 D2쳐� � � 쳐x컴� 쳐퀱4 D2쳐� � � 쳐훫컴좔탠퀱5 D1쳐탠� � � � 읕탠퀱5 D1쳐탠� � � � 쳐퀱6 D0쳐� � � � 쳐퀱6 D0쳐� � � � 읕퀱7 A0쳐� � � � 읕퀱7 A0쳐� � � � o컴�-CE A1쳐� � � � o캑-CE A1쳐� � � � 旼캑A10 2732 A2쳐� � � � 旼캑A10 2732 A2쳐� � � 쳐컴x컴�-OE A3쳐탠쩡컴캑 � 쳐컴x컴�-OE A3쳐탠쩡컴� � � o훫컴퀮11 2 A4쳐� � � � � o훫컴퀮11 2 A4쳐� � � � � 旼탠캑A9 A5쳐� � � � � 旼탠캑A9 A5쳐� � � � � � 읕캑A8 A6쳐� � � � � � 읕캑A8 A6쳐� � � � � � 캑VCC 旼커 A7쳐� � � � � � 캑VCC 旼커 A7쳐� � � � � � 읕컴컨컴좔컴켸 � � � � � 읕컴컨컴좔컴켸 � � � � 읕컴컴컴컴컴컴컴컴컴컴� � � � 읕컴컴컴컴컴컴컴컴컴컴� � � � 旼컴컴컴컴컴컴컴컴컴커 � � � 旼컴컴컴컴컴컴컴컴컴커 � � � � 旼컴컴컴컴컴커 � � � � � 旼컴컴컴컴컴커 � � � � � 旼퀱3 c3h GND쳐 � � � � � 旼퀱3 c3l GND쳐 � � � � � 쳐퀱4 D2쳐� � � � � � 쳐퀱4 D2쳐� � � 쳐훫컴좔탠퀱5 D1쳐탠� � 쳐x컴좔탠퀱5 D1쳐탠� � � � 쳐퀱6 D0쳐� � � � 쳐퀱6 D0쳐� � � � 읕퀱7 A0쳐� � � � 읕퀱7 A0쳐� � � � o캑-CE A1쳐� � � � o캑-CE A1쳐� � � � 旼캑A10 2732 A2쳐� � � � 旼캑A10 2732 A2쳐� � � 쳐컴x컴�-OE A3쳐탠쩡컴캑 � 쳐컴x컴�-OE A3쳐탠쩡컴� � � o훫컴퀮11 3 A4쳐� � � � � o훫컴퀮11 3 A4쳐� � � � � 旼탠캑A9 A5쳐� � � � � 旼탠캑A9 A5쳐� � � � � � 읕캑A8 A6쳐� � � � � � 읕캑A8 A6쳐� � � � � � 캑VCC 旼커 A7쳐� � � � � � 캑VCC 旼커 A7쳐� � � � � � 읕컴컨컴좔컴켸 � � � � � 읕컴컨컴좔컴켸 � � � � 읕컴컴컴컴컴컴컴컴컴컴� � � � 읕컴컴컴컴컴컴컴컴컴컴� � � � � � � � � � 旼컴컴컴컴컴컴컴컴컴커 � � � 旼컴컴컴컴컴컴컴컴컴커 � � � � 旼컴컴컴컴컴커 � � � � � 旼컴컴컴컴컴커 � � � � � 旼퀱3 c4h GND쳐 � � � � � 旼퀱3 c4l GND쳐 � � � � � 쳐퀱4 D2쳐� � � � � � 쳐퀱4 D2쳐� � � 쳐훫컴좔탠퀱5 D1쳐탠� � 쳐x컴좔탠퀱5 D1쳐탠� � � � 쳐퀱6 D0쳐� � � � 쳐퀱6 D0쳐� � � � 읕퀱7 A0쳐� � � � 읕퀱7 A0쳐� � � � o캑-CE A1쳐� � � � o캑-CE A1쳐� � � � 旼캑A10 2732 A2쳐� � � � 旼캑A10 2732 A2쳐� � � 읕컴x컴�-OE A3쳐탠쩡컴켸 � 읕컴x컴�-OE A3쳐탠쩡컴� � o훫컴퀮11 4 A4쳐� � � o훫컴퀮11 4 A4쳐� � � 旼탠캑A9 A5쳐� � � 旼탠캑A9 A5쳐� � � � 읕캑A8 A6쳐� � � � 읕캑A8 A6쳐� � � � 캑VCC 旼커 A7쳐� � � � 캑VCC 旼커 A7쳐� � � � 읕컴컨컴좔컴켸 � � � 읕컴컨컴좔컴켸 � � 쳐컴컴컴컴컴컴컴컴컴컴좔컴컴컴컴컴x컴컨컴컴컴컴컴컴컴컴컴컴켸 � � � � o From Latches LS11 bits of � � Address � � A11 for each set of ROMs � � is sent through glue � � RAM/RAMH switches may � � replace A11 with R/W for � � Static RAM access. � � � o To edge connector (High Data) o To edge connector (Low Data) One set of address address comparison (glue) for each set of two ROM's above. Set consists of one ROM from each bank. 4 sets in total. +5v 컴旼쩡쩡쩡쩡쩡쩡� a b y 旼좔좔좔좔좔좔좔좔� DW from 컴컫컴쩡 � r 퀂 o 4 to 10 decoder h 쿴 쿹 74LS00N � e a r a a a a 퀇b � x 쿹 쿴 quad 2 input � n n m a 1 1 1 1 퀃a � l 퀈 쿴 +nand gates � c a h m 2 3 4 5 쿬n � y = -(a*b) 읕쩡쩡쩡쩡爐爐爐爐�hk � 旼컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴컴커 旼컴컴컴켸 � � � � � � � � o (latch a11) 旼컴컴컴�(ramh)컴컴컴x컴컴훫컴컴컴컴컴� � � � � � � � � 旼컴컴컴컴컴컴컴x컴컴커 � 旼컴x컴컴컴컴컴컴� � � � � � � 쳐x컴컴컴컴컴컴컴훫컴커 � 旼컴컴컴컴커 � � � �袴袴袴袴袴袴x�x�x枯 � � � 넬컴컫쩡컴� � � � 넬컴컫쩡컴엿 � � � 붚컴컫쩡컴� � � � � � � 윱1a 잎 +5쳐 � � � 척1a 잎 +5쵬 � � � 홱b3 잎 +5쳐 � � � � � 읕캑2a 1c쳐컴컴x커 � � 윱1b 4b쳐훫캑 旼x컴큑bi a2촐�x�x袴袴o <(a14 Latch) 旼컴컴�2d 1e쳐컴x캑 � 旼x컴�2b 3b쳐컴캑 � nc큑>bo a1팠�x�x袴袴o <(a13 Latch) � 旼캑2y 1d쳐컴� � � � 읕캑2y 3a쳐커 � � 旼캑a=bo b1팠�x暠 � � 캑GND 1y쳐� � � � � 캑GND 3y첼 � � � 쿻c큑