============================================================================== Programmable Sound Generator ============================================================================== Below is a textual transcription of the AY-3-8912 spec sheet that I found on the web. I have no idea here I found it -- it was laying on my hard-drive, and I thought it would be useful to include. ------------------------------------------------------------------------------ AY-3-8912 vs. AY-3-8914 NOTES ------------------------------------------------------------------------------ Note that the info below is for the AY-3-8912. The Intellivision uses a related part, the AY-3-8914. The primary difference is in the memory map. Here is the PSG's memory map on the Intellivision, and how it maps to the AY-3-8912's register numbers in the documentation below: ADDRESS REGISTER # DESCRIPTION ----------- --------------- ---------------------------------------------- $01F0 R0 Channel A Period (Low 8 bits of 12) $01F1 R2 Channel B Period (Low 8 bits of 12) $01F2 R4 Channel C Period (Low 8 bits of 12) $01F3 R13 Envelope Period (Low 8 bits of 16) $01F4 R1 Channel A Period (High 4 bits of 12) $01F5 R3 Channel B Period (High 4 bits of 12) $01F6 R5 Channel C Period (High 4 bits of 12) $01F7 R14 Envelope Period (High 8 bits of 16) $01F8 R7 Enable Noise/Tone (bits 3-5 Noise : 0-2 Tone) $01F9 R6 Noise Period (5 bits) $01FA R15 Envelope type (4 bits) $01FB R10 Channel A Volume (6 bits) $01FC R11 Channel B Volume (6 bits) $01FD R12 Channel C Volume (6 bits) $01FE R8 ? Controller input (right controller) $01FF R9 ? Controller input (left controller) Note that the AY-3-8914 does provide two I/O ports. On the Intellivision Master Component, these I/O ports interface to the Hand Controllers. ------------------------------------------------------------------------------ INTELLIVISION SPECIFIC DETAILS ------------------------------------------------------------------------------ The NTSC-based Intellivision uses a 3.579545MHz clock and the PAL-based Intellivision uses a 4.00MHz clock. The PSG is driven from a clock signal at half this rate. Internally, the PSG divides down its clock by 16 to determine the final square-wave frequency. The frequency of a tone produced by the Intellivision is therefore given by: 3.579545MHz F_tone = ------------- for NTSC 32*P_channel and 4.000000MHz F_tone = ------------- for PAL 32*P_channel Here, P_channel is the period register setting for the given channel. Envelopes are similar, although the PSG divides down the clock by 256 instead of 16: 3.579545MHz F_envp = ------------- for NTSC 512*P_envp and 4.000000MHz F_envp = ------------- for PAL 512*P_envp Here, P_envp is the period register setting for the envelope generator. Note that F_envp is the frequency for one full cycle (16 steps) of the envelope. The time between each step of the envelope is identical to the time for one full square wave period for a given Period register value. ------------------------------------------------------------------------------ AY-3-8912 SPEC SHEET ------------------------------------------------------------------------------ A2. Programmable Sound Generator AY-3-8912 (from General Instruments data sheet) ------------------------------------------ Interfacing Bus control signals BDIR (Bus DIRection), BC2, BC1 (Bus Control 2,1) are generated directly by the CP1610 series of microprocessors to control all external and internal bus operations in the PSG. While interfacing to a processor other than the CP1610 would simply require simulating these signals, the redundancies in the PSG functions vs. bus control signals can be used to advantage in that only four of the eight possible decoded bus functions are required by the PSG. This could simplify the programming of the bus control signals to the following, which would only require that the processor generate two bus control signals (BDIR and BC1, with BC2 tied to +5V). BDIR BC1 PSG Function 0 0 Inactive 0 1 Read from PSG 1 0 Write to PSG 1 1 Latch address Architecture The AY-3-8910/8912/8913 is a register oriented Programmable Sound Generator. Control commands are issued to the PSG by writing to 16 registers (register addresses are expressed in octal base). Each of the 16 registers is also readable so that the microprocessor can determine present states or stored data values. All functions of the PSG are controlled through the 16 registers which once programmed, generate and sustain the sounds, thus freeing the system processor for other tasks. The basic blocks in the PSG which produce the programmed sounds include: Tone Generators produce the basic square wave tone frequencies for each channel (A,B,C) Noise Generator produces a frequency modulated pseudo random pulse width square wave output Mixers combine the outputs of the Tone Generators and the Noise Generator. One for each channel (A,B,C) Amplitude Control provides the D/A converters with either fixed or variable amplitude pattern. The fixed amplitude is under direct CPU control; the variable amplitude is accomplished by using the output of the Envelope Generator. Envelope Generator produces an envelope pattern which can be used to amplitude modulate the output of each mixer D/A Converters the three D/A converters each produce up to a 16 level output signal as determined by the Amplitude Control In addition, there are two IO ports (A and B) to interface with the outside world. Both ports are available on the AY-3-8910; only IO port A is available on the AY-3-8912; no ports are available on the AY-3-8913. Operation The function of creating or programming a specific sound or sound effect logically follows the control sequence listed: Tone Generator Control (registers R0,R1,R2,R3,R4,R5) The frequency of each square wave generated by the three Tone Generators (one each for Channels A, B and C) is obtained in the PSG by first counting down the input clock by 16, then by further counting down the result by the programmed 12-bit Tone Period value. Each 12-bit value is obtained in the PSG by combining the contents of the relative Coarse and Fine Tune registers: bits 0-3 of the Coarse Tune registers give the Most Significant bits, bits 0-7 of the Fine Tune registers give the Least Significant bits. Channel Coarse Tune Register Fine Tune Register A R1 R0 B R3 R2 C R5 R4 Noise Generator Control (register R6) The frequency of the noise source is obtained by first counting down the input clock by 16, then by further counting down the result by the programmed 5-bit Noise Period value. This 5-bit value consists of the lower 5 bits (b4-b0) of register R6. Mixer Control - IO Enable (register R7) The determination of combining neither/either/both noise and tone frequencies on each channel is made by the state of bits b5-b0 of R7. The direction (input or output) of the two general purpose IO ports is determined by the state of bits b7 and b6. These bits are active low, so a 1 disables, and a 0 enables the function b7 input enable IO port A b6 input enable IO port B b5 noise enable channel C b4 noise enable channel B b3 noise enable channel A b2 tone enable channel C b1 tone enable channel B b0 tone enable channel A Amplitude Control (registers R10,R11,R12) The amplitudes of the signals generated by each of the three D/A converters is determined by the contents of the lower 5 bits (b4-b0) of registers R10, R11 and R12. b5 Amplitude Mode (0: fixed, 1: envelope-variable) b4-b0 4-bit fixed amplitude level Envelope Period Control (registers R13, R14) The frequency of the envelope is obtained by first counting down the input clock by 256, then by further counting down the result by the programmed 16-bit envelope period. This 16-bit value is obtained by combining the contents of the Envelope Coarse (R14) and Fine (R13) Tune registers. Envelope Shape/Cycle Control (register R15) The envelope generator further counts down the envelope frequency by 16, producing a 16-state per cycle envelope pattern as defined by its 4-bit counter output. The particular shape and cycle pattern of any desired envelope is accomplished by controlling the count pattern (count up/ count down) of the 4-bit counter and by defining a single-cycle or repeat-cycle pattern. This envelope shape/cycle control is contained in the lower 4 bits of register R15. Each of these 4 bits controls a function in the envelope generator: b3 Continue b2 Attack b1 Alternate b0 Hold R15 bits Graphic representation of envelope generator output 8-) 00xx \__________________________________ 01xx /|_________________________________ 1000 \|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\ 1001 \__________________________________ 1010 \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ _________________________________ 1011 \| 1100 /|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/ __________________________________ 1101 / 1110 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ 1111 /|_________________________________ D/A Converter operation The D/A conversion is performed in logarithmic steps with a normalized voltage range of from 0 to 1 Volt.