; Properly Defined Local Symbols: ; L701D L7023 L7026 L707A L7086 L7093 L7096 L70A4 ; L70AA L70B9 L70BD L70C0 L70D4 L70DB L70DC L7102 ; L7105 L7112 L7114 L711C L712E L7134 L7149 L714E ; L7156 L7158 L7166 L7167 L716F L717F L718A L7198 ; L71B9 L71CA L71DF L71E7 L724C L7280 L7294 L72B7 ; L72DD L72EA L72F6 L72F9 L7301 L733A L7344 L7357 ; L7367 L7370 L737C L739A L73A2 L73AA L73BD L73BE ; L73C0 L73C4 L73C7 L73D0 L73D7 L73D8 L73DB L73DC ; L73DD L73FD L7409 L741B L7423 L7437 L744E L7455 ; L7456 L7472 L7475 L7478 L747E L7482 L74A0 L74AC ; L74B2 L74B7 L74C3 L74C6 L74E4 L74F8 L7502 L7516 ; L752A L752C L752D L752E L752F L7535 L7556 L755A ; L755C L757C L757F L7584 L7590 L7593 L759F L75A9 ; L75AC L75BB L75C2 L75D1 L75E3 L75ED L75F4 L75F8 ; L7601 L760D L7621 L7624 L7629 L7634 L7637 L763F ; L764A L765E L7666 L7671 L7672 L7679 L7682 L7683 ; L769C L769D L76A3 L76BC L76C3 L76CF L76D2 L7728 ; L772C L774D L775D L7768 L7772 L777A L7783 L778E ; L7798 L779D L77A7 L77B7 L77BA L7808 L780B L7820 ; L7827 L7832 L7833 L7844 L7852 L789B L789D L78AA ; L78BC L78C4 L78D4 L78DE L78EE L78EF L790B L7912 ; L7918 L7933 L7944 L794F L7957 L795B L795F L7984 ; L798D L799C L79FF L7A01 L7A05 L7A09 L7A16 L7A1C ; L7A25 L7A2C L7A87 L7ABE L7AC9 L7ACC L7AD6 L7AE0 ; L7AE3 L7B06 L7B1B L7B23 L7B2E L7B70 L7B78 L7B7A ; L7B8C L7BA1 L7BA2 L7BAC L7BB4 L7BC9 L7BD9 L7BF1 ; L7BF6 L7C1F L7C29 L7C2E L7C2F L7C31 L7C32 L7C48 ; L7C68 L7C69 L7C73 L7C7C L7C93 L7CA0 L7CC6 L7CC7 ; L7CC9 L7CE0 L7D06 L7D1F L7D3B L7D55 L7D56 L7D57 ; L7D5C L7D63 L7D75 L7D93 L7DA5 L7DBB L7DD4 L7DD9 ; L7DE1 L7DEA L7E00 L7E0E L7E38 L7E42 L7E54 L7E67 ; L7E74 L7E89 L7E91 L7E9B L7EA4 L7EA9 L7EB1 L7EB7 ; L7EBF L7EC3 L7EC5 L7ED4 L7EE1 L7EE6 L7EEF L7EF7 ; L7F00 L7F08 L7F10 L7F17 L7F1D L7F22 L7F27 L7F2D ; L7F30 L7F3A L7F42 L7F4A L7F50 L7F57 L7F5C L7F5F ; L7F6E L7F74 L7F78 L7F83 L7F84 L7F85 L7F94 L7F9D ; L7FAB L7FC4 L7FC9 L7FCA L7FDA L7FDB L7FE3 L7FE4 ; L7FE7 L7FF6 ; Improperly Defined Local Symbols: L7053 EQU $7053 L76B4 EQU $76B4 L7A03 EQU $7A03 L7A07 EQU $7A07 ; Global Symbols: G103D EQU $103D G1668 EQU $1668 G16E2 EQU $16E2 G16ED EQU $16ED G1730 EQU $1730 G1731 EQU $1731 G1739 EQU $1739 G1741 EQU $1741 G1745 EQU $1745 G1A83 EQU $1A83 G1DDB EQU $1DDB G1DF8 EQU $1DF8 G1DFB EQU $1DFB G1E23 EQU $1E23 G204A EQU $204A G283D EQU $283D G8084 EQU $8084 ORG $7000 ROMW 10 ;;============================================================================= ;; Initialization code. EXEC jumps here. ;;----------------------------------------------------------------------------- L7000: JSR R4, L7023 ; $7000 0004 0070 0023 [.p#] DECLE $322, $323, $00 ; $7003 0322 0333 0000 L7006: DECLE $01 ; $7006 0001 BIDECLE L7726 ; $7007 0026 0077 (ISR vector) JSR R4, L7134 ; $7009 0004 0070 0134 L700C: BIDECLE L7014, L77BD ; $700C 0014 0070 00BD 0077 JSR R4, L7026 ; $7010 0004 0070 0026 DECLE $000 ; $7013 0000 L7014: MOVR R7, R4 ; $7014 \___ R4 == L7014. SUBI #$0002, R4 ; $7015 / MVII #$000B, R3 ; $7017 \___ Branch to 7025 ADDR R3, R7 ; $7019 / L701A: MOVR R7, R4 ; $701A 00BC [. ] SUBI #$0008, R4 ; $701B 033C 0008 [.. ] L701D: MVII #$0005, R3 ; $701D 02BB 0005 [.. ] ADDR R3, R7 ; $701F 00DF [. ] MOVR R7, R4 ; $7020 00BC [. ] SUBI #$000E, R4 ; $7021 033C 000E [.. ] L7023: MVII #$0002, R3 ; $7023 R3 == 2 L7025: INCR R7 ; $7025 Skip CLRR L7026: CLRR R3 ; $7026 R3 == 0 MVII #$02F1, R6 ; $7027 Reset Stack ptr to $02G1 PSHR R4 ; $7029 Save R4 (return address?) JSR R5, L7637 ; $702A Set $83DA to 0 JSR R5, L7621 ; $702D Sync w/ 6502 side. Leaves $8306=0. JSR R5, G1A83 ; $7030 Clear the PSG. SDBD ; $7033 \ MVII #$83BA, R1 ; $7034 |__ Clear $83BA CLRR R0 ; $7037 | MVO@ R0, R1 ; $7038 / ADDI #$0003, R1 ; $7039 \___ Clear $83BD MVO@ R0, R1 ; $703B / ADDI #$00BB, R1 ; $703C R1 = $8478 MVII #$0006, R0 ; $703E MOVR R7, R4 ; $7040 \___ R4 = $7006 SUBI #$003B, R4 ; $7041 / JSRD R5, G1730 ; $7043 Copy $7006-$700B to $8478-$847D MOVR R5, R1 ; $7046 R5 = $847E SUBI #$0010, R1 ; $7047 R1 = $846E MVII #$0004, R0 ; $7049 \___ Copy $700C-$700F to $846E-$8471 JSR R5, G1730 ; $704B / (chain ISR points to L7726.) JSR R5, L777A ; $704E Make L712E current ISR ($0100) JSR R5, L7114 ; $7051 \___ Write bidecle L73E3 to $834[AB] BIDECLE L73E3, $834A ; / R4 = $834C after? JSR R5, L7535 ; $7058 Flush input FIFO, init FIFO @$8438. JSR R5, L75AC ; $705B \___ RPC: Write $5F to $0340 from DECLE $00, $5F ; / the 6502 side. (Init tty flags) SUBI #$0046, R4 ; $7060 R4 = $8306 JSRE R5, L757C ; $7062 Enable ints and do RPC cmd #0C. DECLE $00C ; Reset input FIFO as $8306 should be 0. ADDI #$0164, R4 ; $7066 R4 = $846A SDBD ; $7068 \ MVI@ R4, R0 ; $7069 | MVO@ R0, R4 ; $706A |-- Copy bidecle at $846[AB] to SWAP R0 ; $706B | $846[CD]. MVO@ R0, R4 ; $706C / JSR R5, L73DB ; $706D \___ Send "display mode reset" DECLE $0300 ; / command to 6502 display driver. SARC R3 ; $7071 \___ If bit 0 of R3 set, skip to BC L707A ; $7072 / L707A below. JSR R5, L711C ; $7074 \ DECLE $002 ; |-- Set bit 2 in $8480. BIDECLE $8480 ; / L707A: SARC R3 ; $707A \___ If bit 0 of R3 clear, skip to BNC L7086 ; $707B / L7086 below. JSR R5, L73D0 ; $707D Display title screen: DECLE $00C ; $7080 CTRL-L (clear the screen) DECLE $143 ; $7081 Cursor to row 3 DECLE $309 ; $7082 Intellivision bootup screen DECLE $104 ; $7083 Cursor to col 4 DECLE $151 ; $7084 Cursor to row 17 DECLE $000 ; $7085 NUL (end of string) L7086: JSR R5, L711C ; $7086 \ DECLE $010 ; |-- Set bit 16?? in $8480 BIDECLE $8480 ; / (does this clear $8480??) JSR R5, L76A3 ; $708C Start recording a tape if 6502 wants PULR R4 ; $708F Restore return address JSR R5, L73C0 ; $7090 Display message from @R4 L7093: JSR R5, L73D8 ; $7093 Display CR + LF L7096: JSR R5, L7166 ; $7096 Clear location $847E and R0. JSR R5, L73DB ; $7099 display "error" DECLE $030A ; "error" SDBD ; $709D MVII #$83F6, R4 ; $709E R4 = $83F6... why? CLRR R2 ; $70A1 R2 = 0... why? B L70AA ; $70A2 L70A4: CMPI #$0008, R2 ; $70A4 037A 0008 [.. ] BGE L70B9 ; $70A6 020D 0011 [.. ] INCR R2 ; $70A8 000A [. ] MVO@ R0, R4 ; $70A9 0260 [. ] L70AA: JSR R5, L752E ; $70AA m MOVR R5, R1 ; $70AD 00A9 [. ] ANDI #$0003, R1 ; $70AE 03B9 0003 [.. ] CMPI #$0001, R1 ; $70B0 0379 0001 [.. ] BEQ L70AA ; $70B2 0224 0009 [.. ] MOVR R5, R1 ; $70B4 00A9 [. ] ANDI #$0038, R1 ; $70B5 03B9 0038 [.8 ] BNEQ L70A4 ; $70B7 022C 0014 [.. ] L70B9: CLRR R1 ; $70B9 01C9 [. ] MVO@ R1, R4 ; $70BA 0261 [. ] B L70C0 ; $70BB 0200 0003 [.. ] L70BD: JSR R5, L752E ; $70BD 0004 0174 012E [...] L70C0: ANDI #$0002, R5 ; $70C0 03BD 0002 [.. ] BEQ L70BD ; $70C2 0224 0006 [.. ] JSR R5, L76A3 ; $70C4 0004 0174 02A3 [...] CMPI #$0003, R0 ; $70C7 0378 0003 [.. ] BEQ L7093 ; $70C9 0224 0037 [.7 ] CMPI #$0005, R0 ; $70CB 0378 0005 [.. ] BNEQ L70D4 ; $70CD 020C 0005 [.. ] JSR R5, L71B9 ; $70CF 0004 0170 01B9 [...] B L7096 ; $70D2 0220 003D [.= ] L70D4: MOVR R2, R1 ; $70D4 0091 [. ] BEQ L7096 ; $70D5 0224 0040 [.@ ] MOVR R7, R4 ; $70D7 00BC [. ] ADDI #$00C1, R4 ; $70D8 02FC 00C1 [.. ] INCR R7 ; $70DA 000F [. ] L70DB: PULR R2 ; $70DB 02B2 [. ] L70DC: SDBD ; $70DC 0001 [. ] MVII #$83F6, R3 ; $70DD 02BB 00F6 0083 [...] SDBD ; $70E0 0001 [. ] MVI@ R4, R1 ; $70E1 02A1 [. ] MOVR R1, R5 ; $70E2 008D [. ] BNEQ L7102 ; $70E3 020C 001D [.. ] SDBD ; $70E5 0001 [. ] MVI@ R4, R5 ; $70E6 02A5 [. ] SDBD ; $70E7 0001 [. ] MVI@ R5, R4 ; $70E8 02AC [. ] TSTR R4 ; $70E9 00A4 [. ] BNEQ L70DC ; $70EA 022C 000F [.. ] JSR R5, L73D0 ; $70EC 0004 0170 03D0 [...] SUB $0049, R4 ; $70EF 0304 0049 [.I ] NEGR R0 ; $70F1 0020 [ ] SUB@ R1, R4 ; $70F2 030C [. ] NEGR R0 ; $70F3 0020 [ ] SUB@ R1, R5 ; $70F4 030D [. ] NEGR R0 ; $70F5 0020 [ ] NEGR R2 ; $70F6 0022 [" ] HLT ; $70F7 0000 [. ] MOVR R3, R4 ; $70F8 009C [. ] JSR R5, L73C0 ; $70F9 0004 0170 03C0 [...] JSR R5, L73DB ; $70FC 0004 0170 03DB [...] NEGR R2 ; $70FF 0022 [" ] B L7093 ; $7100 0220 006E [.n ] L7102: ADDI #$0002, R5 ; $7102 02FD 0002 [.. ] PSHR R2 ; $7104 0272 [. ] L7105: MVI@ R3, R0 ; $7105 0298 [. ] INCR R3 ; $7106 000B [. ] CMP@ R5, R0 ; $7107 0368 [. ] BNEQ L70DB ; $7108 022C 002E [.. ] DECR R2 ; $710A 0012 [. ] BNEQ L7105 ; $710B 022C 0007 [.. ] PULR R2 ; $710D 02B2 [. ] MOVR R7, R5 ; $710E 00BD [. ] SUBI #$0079, R5 ; $710F 033D 0079 [.y ] MOVR R1, R4 ; $7111 008C [. ] L7112: SDBD ; $7112 0001 [. ] MVI@ R4, R7 ; $7113 02A7 [. ] ;;============================================================================= ;; BIDECLE COPY: Store bidecle 1 at location specified by bidecle 2. ;; The JSR for this function is followed by two bidecles. ;;----------------------------------------------------------------------------- L7114: SDBD ; $7114 \___ Get bidecle to store MVI@ R5, R0 ; $7115 / SDBD ; $7116 \___ Get address to store it at MVI@ R5, R4 ; $7117 / MVO@ R0, R4 ; $7118 \ SWAP R0 ; $7119 |-- Store out the bidecle across MVO@ R0, R4 ; $711A / two locations. L711B: MOVR R5, R7 ; $711B 00AF [. ] ;;============================================================================= ;;============================================================================= ;; Set bit X at location Y. ;; X is given by first decle after JSR. ;; Y is given by bidecle after that. ;;----------------------------------------------------------------------------- L711C: PSHR R0 ; $711C 0270 [. ] PSHR R1 ; $711D 0271 [. ] MVI@ R5, R0 ; $711E 02A8 [. ] SDBD ; $711F 0001 [. ] MVI@ R5, R1 ; $7120 02A9 [. ] PSHR R5 ; $7121 0275 [. ] J G16ED ; $7122 0004 0314 02ED [...] ;;============================================================================= L7125: PSHR R0 ; $7125 0270 [. ] PSHR R1 ; $7126 0271 [. ] MVI@ R5, R0 ; $7127 02A8 [. ] SDBD ; $7128 0001 [. ] MVI@ R5, R1 ; $7129 02A9 [. ] PSHR R5 ; $712A 0275 [. ] J G16E2 ; $712B 0004 0314 02E2 [...] ;;============================================================================== ;; Default ISR dispatcher ;;------------------------------------------------------------------------------ L712E: SDBD ; $712E \ MVII #$8479, R5 ; $712F |__ Dispatch to ISR vector in $8478 SDBD ; $7132 | MVI@ R5, R7 ; $7133 / ;;============================================================================== L7134: SDBD ; $7134 0001 [. ] MVII #$1014, R5 ; $7135 02BD 0014 0010 [...] PSHR R5 ; $7138 0275 [. ] MVI@ R4, R0 ; $7139 02A0 [. ] DECR R0 ; $713A 0010 [. ] BPL L716F ; $713B 0203 0032 [.2 ] DECR R4 ; $713D 0014 [. ] MVO@ R0, R4 ; $713E 0260 [. ] SUBI #$0007, R4 ; $713F 033C 0007 [.. ] MVI@ R4, R0 ; $7141 02A0 [. ] SUBI #$012F, R4 ; $7142 033C 012F [.. ] SARC R0 ; $7144 0078 [x ] BC L714E ; $7145 0201 0007 [.. ] BEQ L7158 ; $7147 0204 000F [.. ] L7149: ADDI #$000C, R4 ; $7149 02FC 000C [.. ] SARC R0 ; $714B 0078 [x ] BNC L7156 ; $714C 0209 0008 [.. ] L714E: PSHR R0 ; $714E 0270 [. ] PSHR R4 ; $714F 0274 [. ] JSR R5, L7112 ; $7150 0004 0170 0112 [...] PULR R4 ; $7153 02B4 [. ] PULR R0 ; $7154 02B0 [. ] TSTR R0 ; $7155 0080 [. ] L7156: BNEQ L7149 ; $7156 022C 000E [.. ] L7158: JSR R5, L718A ; $7158 Update "recent input" flag. XOR@ R1, R0 ; $715B 03C8 [. ] BNEQ L7167 ; $715C 020C 0009 [.. ] JSR R5, L7114 ; $715E \ BIDECLE L7170 ; |-- Store L7170 @ $100 (make L7170 BIDECLE $0100 ; / the current ISR.) INCR R7 ; $7165 000F [. ] ;;============================================================================== ;; Clear location $847E and R0 ;;------------------------------------------------------------------------------ L7166: PSHR R5 ; $7166 L7167: CLRR R0 ; $7167 \ PSHR R1 ; $7168 | SDBD ; $7169 |__ Clear location $847E and R0 MVII #$847E, R1 ; $716A | MVO@ R0, R1 ; $716D | PULR R1 ; $716E / L716F: PULR R7 ; $716F ;;============================================================================== ;;============================================================================== ;; STIC Screen-blank ISR. ;;------------------------------------------------------------------------------ L7170 PSHR R5 ; $7170 JSR R5, L718A ; $7171 Update "recent input" flag MVII #$002C, R3 ; $7174 Point R3 at STIC border color reg. MOVR R1, R2 ; $7176 R1 = R2 = $8307 ADDI #$00F7, R2 ; $7177 Point R2 to $83FE MVI@ R3, R5 ; $7179 Get current border color. CMP@ R2, R0 ; $717A (Note: R0 == 0). Is @$83FE == 0? MVO@ R0, R3 ; $717B Make the screen black. BNEQ L717F ; $717C If @$83FE was non-zero, skip next. MVO@ R5, R2 ; $717E Save previous border color in $83FE. L717F: XOR@ R1, R0 ; $717F Check the "recent input" flag. BEQ L716F ; $7180 If it's zero (no input), just return. MVI@ R2, R0 ; $7182 Get border color from @$83FE MVO@ R0, R3 ; $7183 Save it to STIC border color reg. CLRR R0 ; $7184 \ Clear display-blanked flag @$83FE MVO@ R0, R2 ; $7185 / JSR R5, L777A ; $7186 Make L712E current ISR. PULR R7 ; $7189 Return from ISR. ;;============================================================================== ;;============================================================================== ;; Set "recent input" flag at $8307 to 1 if either controller is pressed. ;;------------------------------------------------------------------------------ L718A: SDBD ; $718A \___ Point to flag at $8307 MVII #$8307, R1 ; $718B / MVII #$01FE, R4 ; $718E \ MVI@ R4, R0 ; $7190 |-- Read both hand controllers into XOR@ R4, R0 ; $7191 / one word. BEQ L7198 ; $7192 If both read as $00FF, return. MVII #$0001, R0 ; $7194 \ MVO@ R0, R1 ; $7196 |-- Set flag at $8307 and clear R0. DECR R0 ; $7197 / L7198: MOVR R5, R7 ; $7198 Return. ;;============================================================================== L719A: BIDECLE L725A ; TAPE BIDECLE L720D ; CARTRIDGE BIDECLE L71AD ; INDEX BIDECLE L72BF ; RESUME BIDECLE L732A ; EJECT BIDECLE L730E ; CLEAN BIDECLE L71F4 ; SCREEN BIDECLE $83A4 ; (Cart plugged into keyboard ?) BIDECLE $0000 BIDECLE $83B8 ; ?? ptr to a vector in 6502 space ;;============================================================================== ;; Menu Entry for INDEX ;;------------------------------------------------------------------------------ L71AD: BIDECLE L71B9 BYTE "INDEX", 0 ;------ "List Commands", 0 DECLE $35A, " " ; "List " DECLE $359, 0 ; "Commands", 0 L71B9: PSHR R5 ; $71B9 0275 [. ] JSR R5, L73D0 ; $71BA 0004 0170 03D0 [...] INCR R4 ; $71BD 000C [. ] NEGR R0 ; $71BE 0020 [ ] CMP@ R4, R0 ; $71BF 0360 [. ] SUB@ R4, R1 ; $71C0 0321 [. ] SUB@ R3, R1 ; $71C1 0319 [. ] SUB@ R4, R3 ; $71C2 0323 [. ] HLT ; $71C3 0000 [. ] MOVR R7, R5 ; $71C4 00BD [. ] SUBI #$002C, R5 ; $71C5 033D 002C [., ] PSHR R5 ; $71C7 0275 [. ] B L71DF ; $71C8 0200 0015 [.. ] L71CA: ADDI #$0002, R4 ; $71CA 02FC 0002 [.. ] MOVR R4, R1 ; $71CC 00A1 [. ] MVI@ R1, R1 ; $71CD 0289 [. ] TSTR R1 ; $71CE 0089 [. ] BEQ L71E7 ; $71CF 0204 0016 [.. ] PSHR R5 ; $71D1 0275 [. ] JSR R5, L73C0 ; $71D2 0004 0170 03C0 [...] JSR R5, L73D0 ; $71D5 0004 0170 03D0 [...] SUBR R1, R4 ; $71D8 010C [. ] ADCR R5 ; $71D9 002D [- ] NEGR R0 ; $71DA 0020 [ ] HLT ; $71DB 0000 [. ] JSR R5, L73C0 ; $71DC 0004 0170 03C0 [...] L71DF: JSR R5, L73D0 ; $71DF 0004 0170 03D0 [...] INCR R2 ; $71E2 000A [. ] INCR R2 ; $71E3 000A [. ] SUBR R0, R2 ; $71E4 0102 [. ] HLT ; $71E5 0000 [. ] PULR R5 ; $71E6 02B5 [. ] L71E7: SDBD ; $71E7 0001 [. ] MVI@ R5, R4 ; $71E8 02AC [. ] TSTR R4 ; $71E9 00A4 [. ] BNEQ L71CA ; $71EA 022C 0021 [.! ] SDBD ; $71EC 0001 [. ] MVI@ R5, R4 ; $71ED 02AC [. ] SDBD ; $71EE 0001 [. ] MVI@ R4, R5 ; $71EF 02A5 [. ] TSTR R5 ; $71F0 00AD [. ] BNEQ L71E7 ; $71F1 022C 000B [.. ] PULR R7 ; $71F3 02B7 [. ] ;;============================================================================== ;; Menu Entry for SCREEN ;;------------------------------------------------------------------------------ L71F4: BIDECLE L7204 BYTE "SCREEN", 0 ;------ "Enter Typewriter Mode", 0 DECLE $35D, " " ; "Enter " DECLE $360, $312, " " ; "Typewriter " DECLE $35E, 0 ; "Mode", 0 L7204: JSR R5, L73DB ; $7204 0004 0170 03DB [...] XOR $0004, R7 ; $7207 03C7 0004 [.. ] \ RRC R0 ; $7209 0070 [p ] | CMP@ R2, R7 ; $720A 0357 [. ] |-- ??? CLRC ; $720B 0006 [. ] | ADDR R0, R0 ; $720C 00C0 [. ] / ;;============================================================================== ;; Menu Entry for CARTRIDGE ;;------------------------------------------------------------------------------ L720D: BIDECLE L721F ; $720D 001F 0072 BYTE "CARTRIDGE",0 ; $720F DECLE $353, " " ; "Start " DECLE $346, " " ; "Cartridge " DECLE $357, 0 ; "Program", 0 L721F: MVII #$0050, R1 ; $721F \ SWAP R1 ; $7221 | Look for viable ROM at location MVI@ R1, R0 ; $7222 |__ $5000 (eg. 6 MSBs are zero) SWAP R0 ; $7223 | If none is found, reset and ANDI #$00FC, R0 ; $7224 | complain to the user. BNEQ L724C ; $7226 / PSHR R1 ; $7228 \ JSR R5, L763F ; $7229 |-- Reset 6502 side and have it BIDECLE $C003 ; / vector to $C003. (Slave mode?) JSR R5, L737C ; $722E \___ ? DECLE $000 ; $7231 / Also clear location $8480 PULR R5 ; $7232 \ ($5000 from above) SDBD ; $7233 | MVI@ R5, R0 ; $7234 |-- Detect special KBD cart? DECR R0 ; $7235 | BEQ L73D8 ; $7236 / MVII #$02F0, R1 ; $7238 \ ADDI #$0012, R5 ; $723A |-- Set UDB pointer @ $2F0 (for MVO@ R5, R1 ; $723C / EXEC cart header-reading utils) JSR R5, L75AC ; $723D \___ Write $D0 to $340 on 6502 side. DECLE $000, $0D0 / JSRD R5, L7114 ; $7242 \___ write "$1126" to $847[9A] BIDECLE $1126, $8479 ; / (address of EXEC's default ISR) J G103D ; $7249 Do EXEC's normal cart bootup seq. L724C: JSR R4, L701D ; $724C Reset and tell user we didn't ; find a cartridge. ;------ "\r\n ? I don't see a cartridge", 0 DECLE $304, "I " ; "\r\n ? I " DECLE $30C, " " ; "don't " DECLE $30E, " " ; "see " DECLE "a ", $306, 0 ; "a cartridge", 0 ;;============================================================================== ;;============================================================================== ;; Menu Entry for TAPE ;;------------------------------------------------------------------------------ L725A: DECLE L7267 DECLE "TAPE", 0 ;------ "Start Cassette Program" DECLE $353, " ", ; "Start " DECLE $347, " ", ; "Cassette " DECLE $357, 0 ; "Program", 0 L7267: JSR R5, L7666 ; $7267 \ DECLE $001 ; $726A |-- Sense cassette tape? BNEQ L7280 ; $726B / JSR R5, L769C ; $726D JSR R4, L701D ; $7270 Reset and tell user we didn't find ; a cassette tape. ;------ "\r\n ? I can't see the cassette tape", 0 DECLE $304, "I " ; "\r\n ? I " DECLE $30F, " " ; "can't " DECLE $30E, " " ; "see " DECLE $316, " " ; "the " DECLE $307, " " ; "cassette " DECLE $308, 0 ; "tape", 0 ;;============================================================================== ;;============================================================================== ;; ?? ;;------------------------------------------------------------------------------ L7280: JSR R5, L7683 ; $7280 0004 0174 0283 [...] JSR R5, L737C ; $7283 0004 0170 037C [...] DECLE $140 ; set bits 6, 9 in $8480 JSR R5, L763F ; $7287 \___ Re-init 6502 side and have it BIDECLE $C003 ; / vector over to $C003. MVII #$0001, R1 ; $728C 02B9 0001 [.. ] JSR R5, L7601 ; $728E 0004 0174 0201 [...] INCR R5 ; $7291 000D [. ] MVII #$0258, R1 ; $7292 02B9 0258 [.. ] L7294: DECR R1 ; $7294 0011 [. ] BEQ L72B7 ; $7295 0204 0020 [. ] JSR R5, L7666 ; $7297 0004 0174 0266 [...] TSTR R0 ; $729A 0080 [. ] BNEQ L7294 ; $729B 022C 0008 [.. ] JSR R5, L7679 ; $729D 0004 0174 0279 [...] BC L72B7 ; $72A0 0201 0015 [.. ] JSR R5, L73D0 ; $72A2 0004 0170 03D0 [...] SUB $0104, R1 ; $72A5 0301 0104 [.. ] CMP@ R2, R0 ; $72A7 0350 [. ] SUB@ R1, R3 ; $72A8 030B [. ] SUB $0000, R1 ; $72A9 0301 0000 [.. ] JSR R5, L764A ; $72AB 0004 0174 024A [...] JSR R5, L7671 ; $72AE 0004 0174 0271 [...] BC L72B7 ; $72B1 0201 0004 [.. ] ADDI #$012D, R4 ; $72B3 02FC 012D [.. ] SDBD ; $72B5 0001 [. ] MVI@ R4, R7 ; $72B6 02A7 [. ] L72B7: JSR R4, L7026 ; $72B7 0004 0070 0026 [.p&] SUB $0348, R4 ; $72BA 0304 0348 [.. ] NEGR R0 ; $72BC 0020 [ ] SUB $0000, R5 ; $72BD 0305 0000 [.. ] ;;============================================================================== ;; Menu Entry for RESUME ;;------------------------------------------------------------------------------ L72BF: BIDECLE L72CF DECLE "RESUME", 0 ;------ "Return to Program", 0 DECLE $35B, " " ; "Return " DECLE "to " ; "to " DECLE $357, 0 ; "Program", 0 L72CF: SDBD ; $72CF 0001 [. ] MVII #$8480, R4 ; $72D0 02BC 0080 0084 [...] MVI@ R4, R2 ; $72D3 02A2 [. ] SUBI #$001B, R4 ; $72D4 033C 001B [.. ] SARC R2, 2 ; $72D6 007E [~ ] BOV L72DD ; $72D7 0202 0004 [.. ] BMI L7301 ; $72D9 020B 0026 [.& ] BC L72EA ; $72DB 0201 000D [.. ] L72DD: JSR R4, L7026 ; $72DD 0004 0070 0026 [.p&] SUB $0351, R4 ; $72E0 0304 0351 [.. ] ADCR R4 ; $72E2 002C [, ] NEGR R0 ; $72E3 0020 [ ] SLL R1 ; $72E4 0049 [I ] NEGR R0 ; $72E5 0020 [ ] SUB@ R1, R7 ; $72E6 030F [. ] NEGR R0 ; $72E7 0020 [ ] SUB@ R2, R4 ; $72E8 0314 [. ] HLT ; $72E9 0000 [. ] L72EA: ANDI #$0008, R2 ; $72EA 03BA 0008 [.. ] BEQ L72F6 ; $72EC 0204 0008 [.. ] SUBI #$00C6, R4 ; $72EE 033C 00C6 [.. ] JSR R5, L757C ; $72F0 0004 0174 017C [...] INCR R2 ; $72F3 000A [. ] B L72F9 ; $72F4 0200 0003 [.. ] L72F6: JSR R5, L7634 ; $72F6 0004 0174 0234 [...] L72F9: JSR R5, L772C ; $72F9 0004 0174 032C [...] PULR R5 ; $72FC 02B5 [. ] SDBD ; $72FD 0001 [. ] MVII #$8468, R4 ; $72FE 02BC 0068 0084 [.h.] L7301: SDBD ; $7301 0001 [. ] MVII #$8480, R3 ; $7302 02BB 0080 0084 [...] MVI@ R3, R0 ; $7305 0298 [. ] MOVR R0, R2 ; $7306 0082 [. ] ANDI #$03E3, R2 ; $7307 03BA 03E3 [.. ] MVO@ R2, R3 ; $7309 025A [. ] SLR R0, 2 ; $730A 0064 [d ] SARC R0, 2 ; $730B 007C [| ] SDBD ; $730C 0001 [. ] MVI@ R4, R7 ; $730D 02A7 [. ] ;;============================================================================= ;;============================================================================= ;; Menu Entry for CLEAN ;;----------------------------------------------------------------------------- L730E: BIDECLE L731E DECLE "CLEAN", 0 ;------ "Enter Head Cleaning Mode", 0 DECLE $35D, " " ; "Enter " DECLE $35F, " " ; "Head " DECLE $358, " " ; "Cleaning " DECLE $35E, 0 ; "Mode", 0 L7315: PSHR R5 ; $731E 0275 [. ] JSR R5, L733A ; $731F 0004 0170 033A [...] CLRR R1 ; $7322 01C9 [. ] COMR R1 ; $7323 0019 [. ] SLR R1 ; $7324 0061 [a ] JSR R5, L7601 ; $7325 0004 0174 0201 [...] TCI ; $7328 0005 [. ] PULR R7 ; $7329 02B7 [. ] ;;============================================================================= ;;============================================================================= ;; Menu Entry for EJECT ;;----------------------------------------------------------------------------- L732A: BIDECLE L733A DECLE "EJECT", 0 ;------ "Rewind and Eject Tape", 0 DECLE $343, " " ; "Rewind " DECLE $31C, " " ; "and " DECLE $355, " " ; "Eject " DECLE $348, 0 ; "Tape", 0 L733A: PSHR R5 ; $733A 0275 [. ] JSR R5, L7666 ; $733B 0004 0174 0266 [...] SDBD ; $733E 0001 [. ] BEQ L7344 ; $733F 0204 0003 [.. ] JSR R5, L7683 ; $7341 0004 0174 0283 [...] L7344: JSR R5, L769D ; $7344 0004 0174 029D [...] JSR R5, L737C ; $7347 0004 0170 037C [...] DECLE $000 ; clear $8480 JSR R5, L73DB ; $734B 0004 0170 03DB [...] XOR $033C, R2 ; $734E 03C2 033C [.. ] COMR R0 ; $7350 0018 [. ] B L7357 ; $7351 0200 0004 [.. ] JSR R5, L739A ; $7353 0004 0170 039A [...] DECLE $002 L7357: SDBD ; $7357 0001 [. ] MVII #$8435, R2 ; $7358 02BA 0035 0084 [.5.] MOVR R2, R3 ; $735B 0093 [. ] INCR R3 ; $735C 000B [. ] CLRR R1 ; $735D 01C9 [. ] MVO@ R1, R2 ; $735E 0251 [. ] MVO@ R1, R3 ; $735F 0259 [. ] JSR R5, L757C ; $7360 0004 0174 017C [...] INCR R2 ; $7363 000A [. ] JSR R5, L7535 ; $7364 0004 0174 0135 [...] L7367: CMP@ R2, R1 ; $7367 0351 [. ] BNEQ L7370 ; $7368 020C 0006 [.. ] JSR R5, L7502 ; $736A 0004 0174 0102 [...] BC L7370 ; $736D 0201 0001 [.. ] MVO@ R0, R2 ; $736F 0250 [. ] L7370: MVI@ R3, R0 ; $7370 0298 [. ] TSTR R0 ; $7371 0080 [. ] BEQ L7367 ; $7372 0224 000C [.. ] JSR R5, L73AA ; $7374 0004 0170 03AA [...] BC L7367 ; $7377 0221 0011 [.. ] MVO@ R1, R3 ; $7379 0259 [. ] B L7367 ; $737A 0220 0014 [.. ] ;;============================================================================= ;; Initiate shutdown of 6502 side so we can go to cart? ;;----------------------------------------------------------------------------- L737C: PSHR R5 ; $737C 0275 [. ] JSR R5, L75F4 ; $737D 0004 0174 01F4 [...] BYTE $01, $0D, $0A ; copy 10 bytes to locations "PEEK($352)+13" ; through "PEEK($352)+22" via RPC cmd #4. BYTE $05, $03, $00, $00, $00, $85, $FF, $BF, $00, $0E JSR R5, L7114 ; $738D \___ Write bidecle $711B to $8468 BIDECLE L711B, $8468 ; / ;notes: L711B is a "JR R5" (return) instruction ; $8468 is some sort of jump vector (Ref: $72FE/$730C) SUBI #$00B2, R4 ; $7394 \ R4==$83B8 CLRR R0 ; $7396 |__ Clear 6502 ISR vector at MVO@ R0, R4 ; $7397 | $83B8 (shut down 6502 in MVO@ R0, R4 ; $7398 / prep for cart?) PULR R5 ; $7399 Restore ptr to caller's args ;fallthru ;;============================================================================= ;; Store decle from caller's args to $8480. ;;----------------------------------------------------------------------------- L739A: MVI@ R5, R0 ; $739A \ PSHR R5 ; $739B | Store decle from caller's SDBD ; $739C |-- args to $8480. (why?) MVII #$8480, R5 ; $739D | MVO@ R0, R5 ; $73A0 / PULR R7 ; $73A1 Return ;;============================================================================= ;;============================================================================= ;; Store a decle to the output FIFO if flags in $8340 permit. ;;----------------------------------------------------------------------------- L73A2: SDBD ; $73A2 \ MVII #$8340, R3 ; $73A3 |-- Get flags word @ $8340 MVI@ R3, R3 ; $73A6 / SARC R3 ; $73A7 Check bit 0. BNC L73D7 ; $73A8 If clear, return. ;fall thru ;;============================================================================= ;; Queue character for display. Play BEL character for ASCII 7. ;; Character in R?. returns success/fail in C ;;----------------------------------------------------------------------------- L73AA: PSHR R5 ; $73AA Save return address. PSHR R4 ; $73AB Save R4. SDBD ; $73AC \___ Point to output FIFO @$8315 MVII #$8315, R4 ; $73AD / JSR R5, L779D ; $73B0 Try to enqueue a decle BC L73BE ; $73B3 If failed, return w/ carry set. CMPI #$0007, R0 ; $73B5 Was it a BEL character? BNEQ L73BD ; $73B7 No: Clear error and return. MVII #$0018, R4 ; $73B9 \___ Play a BEL sound on PSG. B L74C6 ; $73BB / L73BD: CLRC ; $73BD 0006 [. ] L73BE: PULR R4 ; $73BE 02B4 [. ] PULR R7 ; $73BF 02B7 [. ] ;;============================================================================= ;;============================================================================= ;; Display character string @R4. ;;----------------------------------------------------------------------------- L73C0: PSHR R5 ; $73C0 Save return address PSHR R0 ; $73C1 Save R0 B L73C7 ; $73C2 Skip first JSR. L73C4: JSR R5, L73DC ; $73C4 Display the character L73C7: MVI@ R4, R0 ; $73C7 Get next character TSTR R0 ; $73C8 Is it NUL? BNEQ L73C4 ; $73C9 Loop until NUL. PULR R0 ; $73CB Restore R0 PULR R7 ; $73CC Return. ;;============================================================================= ;;============================================================================= ;; Display a CTRL-L. ;;----------------------------------------------------------------------------- L73CD: MVII #$000C, R0 ; $73CD \___ Branch to L73DC below to display ADDR R0, R7 ; $73CF / ASCII 12 (CTRL-L -- clear disp) ;;============================================================================= ;;============================================================================= ;; Display string after JSR. ;;----------------------------------------------------------------------------- L73D0: PSHR R4 ; $73D0 Save R4 MOVR R5, R4 ; $73D1 Save return address in R4 JSR R5, L73C0 ; $73D2 Display the string. MOVR R4, R5 ; $73D5 Return to just after string. PULR R4 ; $73D6 Restore R4 L73D7: MOVR R5, R7 ; $73D7 Return ;;============================================================================= ;;============================================================================= ;; Display a CR + LF. ;;----------------------------------------------------------------------------- L73D8: MVII #$0301, R0 ; $73D8 String table entry for CR + LF. INCR R7 ; $73DA Skip MVI@. (L73DC) ;fall-thru ;;============================================================================= ;; Display character. Get character to display from @R5 ;;----------------------------------------------------------------------------- L73DB: MVI@ R5, R0 ; $73DB Get character to display @R5 ;;============================================================================= ;; Display character. Character to display in R0. ;;----------------------------------------------------------------------------- L73DC: PSHR R5 ; $73DC remember return address L73DD: JSR R5, L73AA ; $73DD \___ Enqueue character. Loop BC L73DD ; $73E0 / until successful. PULR R7 ; $73E2 Return. ;;============================================================================= L73E3: PSHR R5 ; $73E3 0275 [. ] SUBI #$0044, R4 ; $73E4 033C 0044 [.D ] JSR R5, L7783 ; $73E6 0004 0174 0383 [...] BC L752D ; $73E9 0201 0142 [.. ] ADDI #$0179, R4 ; $73EB 02FC 0179 [.. ] MVO@ R0, R4 ; $73ED 0260 [. ] JSR R5, L74E4 ; $73EE 0004 0174 00E4 [...] MOVR R5, R1 ; $73F1 00A9 [. ] SUBI #$0142, R4 ; $73F2 033C 0142 [.. ] MVI@ R4, R3 ; $73F4 02A3 [. ] MOVR R3, R2 ; $73F5 009A [. ] SARC R2, 2 ; $73F6 007E [~ ] BNOV L73FD ; $73F7 020A 0004 [.. ] MOVR R1, R5 ; $73F9 008D [. ] ANDI #$0020, R5 ; $73FA 03BD 0020 [. ] SUBR R5, R0 ; $73FC 0128 [. ] L73FD: ANDI #$0004, R3 ; $73FD 03BB 0004 [.. ] BEQ L7409 ; $73FF 0204 0008 [.. ] CMPI #$0015, R0 ; $7401 0378 0015 [.. ] BEQ L7475 ; $7403 0204 0070 [.p ] CMPI #$007F, R0 ; $7405 0378 007F [.. ] BEQ L747E ; $7407 0204 0075 [.u ] L7409: ADDI #$00F7, R4 ; $7409 02FC 00F7 [.. ] JSR R5, L779D ; $740B 0004 0174 039D [...] BC L7423 ; $740E 0201 0013 [.. ] JSR R5, L74B7 ; $7410 0004 0174 00B7 [...] MOVR R1, R5 ; $7413 008D [. ] ANDI #$0004, R5 ; $7414 03BD 0004 [.. ] BNEQ L741B ; $7416 020C 0003 [.. ] JSR R5, L73A2 ; $7418 0004 0170 03A2 [...] L741B: SARC R1, 2 ; $741B 007D [} ] BNOV L7423 ; $741C 020A 0005 [.. ] DECR R4 ; $741E 0014 [. ] MVI@ R4, R5 ; $741F 02A5 [. ] INCR R5 ; $7420 000D [. ] DECR R4 ; $7421 0014 [. ] MVO@ R5, R4 ; $7422 0265 [. ] L7423: ADDI #$0047, R4 ; $7423 02FC 0047 [.G ] MOVR R4, R3 ; $7425 00A3 [. ] SUBI #$0003, R0 ; $7426 0338 0003 [.. ] BNEQ L7455 ; $7428 020C 002B [.+ ] XOR@ R3, R0 ; $742A 03D8 [. ] BNEQ L7437 ; $742B 020C 000A [.. ] MVII #$003C, R0 ; $742D 02B8 003C [.< ] MVO@ R0, R3 ; $742F 0258 [. ] JSR R5, L711C ; $7430 0004 0170 011C [...] JSR R4, G8084 ; $7433 0004 0080 0084 [...] PULR R7 ; $7436 02B7 [. ] L7437: JSR R5, L7456 ; $7437 0004 0174 0056 [..V] JSR R5, L711C ; $743A 0004 0170 011C [...] DECLE $008 ; BIDECLE $8480 ; INCR R3 ; $7440 000B [. ] MVI@ R3, R2 ; $7441 029A [. ] SWAP R2, 2 ; $7442 0046 [F ] BMI L752D ; $7443 020B 00E8 [.. ] SUBI #$0003, R6 ; $7445 033E 0003 [.. ] ANDI #$0050, R2 ; $7447 03BA 0050 [.P ] BNEQ L744E ; $7449 020C 0003 [.. ] JSR R5, L76C3 ; $744B 0004 0174 02C3 [...] L744E: PULR R5 ; $744E 02B5 [. ] SDBD ; $744F 0001 [. ] MVII #$846E, R4 ; $7450 02BC 006E 0084 [.n.] SDBD ; $7453 0001 [. ] MVI@ R4, R7 ; $7454 02A7 [. ] L7455: PULR R5 ; $7455 02B5 [. ] L7456: CLRR R2 ; $7456 01D2 [. ] MVO@ R2, R3 ; $7457 025A [. ] CMP@ R3, R2 ; $7458 035A [. ] BNEQ L7456 ; $7459 022C 0004 [.. ] MOVR R5, R7 ; $745B 00AF [. ] PSHR R5 ; $745C 0275 [. ] SDBD ; $745D 0001 [. ] MVII #$847E, R2 ; $745E 02BA 007E 0084 [.~.] MVO@ R7, R2 ; $7461 0257 [. ] JSR R5, L76C3 ; $7462 0004 0174 02C3 [...] SDBD ; $7465 0001 [. ] MVII #$8480, R5 ; $7466 02BD 0080 0084 [...] MVI@ R5, R2 ; $7469 02AA [. ] SLR R2, 2 ; $746A 0066 [f ] SARC R2, 2 ; $746B 007E [~ ] ANDI #$0008, R2 ; $746C 03BA 0008 [.. ] BNEQ L7472 ; $746E 020C 0002 [.. ] BC L744E ; $7470 0221 0023 [.# ] L7472: J L7167 ; $7472 0004 0370 0167 [...] L7475: JSR R5, L74B7 ; $7475 0004 0174 00B7 [...] L7478: JSR R5, L7482 ; $7478 0004 0174 0082 [...] BNC L7478 ; $747B 0229 0004 [.. ] PULR R7 ; $747D 02B7 [. ] L747E: JSR R5, L74B7 ; $747E 0004 0174 00B7 [...] INCR R7 ; $7481 000F [. ] L7482: PSHR R5 ; $7482 0275 [. ] SDBD ; $7483 0001 [. ] MVII #$8438, R4 ; $7484 02BC 0038 0084 [.8.] MVI@ R4, R3 ; $7487 02A3 [. ] MVI@ R4, R1 ; $7488 02A1 [. ] CMPR R1, R3 ; $7489 014B [. ] BEQ L752D ; $748A return. DECR R4 ; $748C 0014 [. ] ADDR R4, R1 ; $748D 00E1 [. ] DECR R1 ; $748E 0011 [. ] MVI@ R1, R0 ; $748F 0288 [. ] JSR R5, L74E4 ; $7490 0004 0174 00E4 [...] MOVR R5, R2 ; $7493 00AA [. ] SETC ; $7494 0007 [. ] ANDI #$0002, R5 ; $7495 03BD 0002 [.. ] BNEQ L752D ; $7497 return. SUBR R4, R1 ; $7499 0121 [. ] CMPI #$0003, R1 ; $749A 0379 0003 [.. ] BPL L74A0 ; $749C 0203 0002 [.. ] MVII #$002D, R1 ; $749E 02B9 002D [.- ] L74A0: MVO@ R1, R4 ; $74A0 0261 [. ] CMPI #$0009, R0 ; $74A1 0378 0009 [.. ] CLRC ; $74A3 0006 [. ] BNEQ L74AC ; $74A4 020C 0006 [.. ] MVII #$001F, R0 ; $74A6 02B8 001F [.. ] ANDI #$0004, R2 ; $74A8 03BA 0004 [.. ] BEQ L74B2 ; $74AA 0204 0006 [.. ] L74AC: ANDI #$0005, R2 ; $74AC 03BA 0005 [.. ] BNEQ L752D ; $74AE return MVII #$007F, R0 ; $74B0 02B8 007F [.. ] L74B2: JSR R5, L73A2 ; $74B2 0004 0170 03A2 [...] CLRC ; $74B5 0006 [. ] PULR R7 ; $74B6 02B7 [. ] L74B7: PSHR R5 ; $74B7 0275 [. ] SDBD ; $74B8 0001 [. ] MVII #$8340, R5 ; $74B9 02BD 0040 0083 [.@.] MVI@ R5, R5 ; $74BC 02AD [. ] ANDI #$0008, R5 ; $74BD 03BD 0008 [.. ] BNEQ L74C3 ; $74BF 020C 0002 [.. ] PULR R7 ; $74C1 02B7 [. ] PSHR R5 ; $74C2 0275 [. ] L74C3: PSHR R4 ; $74C3 0274 [. ] MVII #$0002, R4 ; $74C4 02BC 0002 [.. ] L74C6: PSHR R0 ; $74C6 0270 [. ] MVII #$01F0, R5 ; $74C7 02BD 01F0 [.. ] ADDI #$0020, R0 ; $74C9 02F8 0020 [. ] MVO@ R0, R5 ; $74CB 0268 [. ] MVII #$01F3, R5 ; $74CC 02BD 01F3 [.. ] CLRR R0 ; $74CE 01C0 [. ] MVO@ R0, R5 ; $74CF 0268 [. ] MVO@ R0, R5 ; $74D0 0268 [. ] MVII #$01F7, R5 ; $74D1 02BD 01F7 [.. ] MVO@ R4, R5 ; $74D3 026C [. ] MVII #$003E, R4 ; $74D4 02BC 003E [.> ] MVO@ R4, R5 ; $74D6 026C [. ] MVII #$01FB, R5 ; $74D7 02BD 01FB [.. ] MVII #$0030, R4 ; $74D9 02BC 0030 [.0 ] MVO@ R4, R5 ; $74DB 026C [. ] MVO@ R0, R5 ; $74DC 0268 [. ] MVO@ R0, R5 ; $74DD 0268 [. ] MVII #$01FA, R5 ; $74DE 02BD 01FA [.. ] MVO@ R0, R5 ; $74E0 0268 [. ] PULR R0 ; $74E1 02B0 [. ] PULR R4 ; $74E2 02B4 [. ] PULR R7 ; $74E3 02B7 [. ] ;;============================================================================= ;; Look up a 5-bit value from table ;;----------------------------------------------------------------------------- L74E4: PSHR R5 ; $74E4 Save Return address PSHR R1 ; $74E5 Save R1 PSHR R0 ; $74E6 Save R0 SDBD ; $74E7 \ MVII #$8470, R5 ; $74E8 | SDBD ; $74EB |-- Get table pointer from $8470 MVI@ R5, R1 ; $74EC | into R1 and R5 both. ($77BD usu) MOVR R1, R5 ; $74ED / SARC R0 ; $74EE \___ Put LSB of argument into LSB of RLC R1 ; $74EF / R1 (temporary storage?) ADDR R0, R5 ; $74F0 Offset into lookup table. RRC R1 ; $74F1 Restore R1, LSB of arg to carry. MVI@ R5, R1 ; $74F2 Use R5 value for table lookup. BNC L74F8 ; $74F3 \ SLR R1, 2 ; $74F5 | Use LSB of arg to select lo or SLR R1, 2 ; $74F6 |-- high "NICKLE" of DECLE we looked SLR R1 ; $74F7 | up. 0==Lo half, 1==Hi half. L74F8: ANDI #$001F, R1 ; $74F8 / PULR R0 ; $74FA Get original argument. MVII #$001F, R5 ; $74FB \ CMPR R0, R5 ; $74FD |-- Set LSB of result if orig. arg RLC R1 ; $74FE / was >= $1F. MOVR R1, R5 ; $74FF Return result in R5 PULR R1 ; $7500 Restore R1 PULR R7 ; $7501 Return. ;;============================================================================= ;;============================================================================= ;; Read and decode a DECLE from FIFO @$8438, non-blocking. ;;----------------------------------------------------------------------------- L7502: PSHR R5 ; $7502 Save R5 PSHR R4 ; $7503 Save R4 EIS ; $7504 Enable ints SDBD ; $7505 \ MVII #$8340, R4 ; $7506 | MVI@ R4, R5 ; $7509 |-- Test bit 2 at $8340. Leave ADDI #$00F7, R4 ; $750A | R4==$8438. (FIFO pointer?) ANDI #$0004, R5 ; $750C / BEQ L7516 ; $750E If Bit 2 clear, goto L7516 DECR R4 ; $7510 \ MVI@ R4, R5 ; $7511 |__ If $8437==0, return w/ C==1 CMPI #$0000, R5 ; $7512 | BEQ L752C ; $7514 / L7516: JSR R5, L7783 ; $7516 \___ Get a DECLE from FIFO @$8438. BC L752C ; $7519 / Return if none ready. JSR R5, L74E4 ; $751B Decode DECLE via tbl $8470? PSHR R5 ; $751E Save decoded value to stack. ANDI #$0002, R5 ; $751F \___ If bit #1's set, just return it. BEQ L752A ; $7521 / DECR R4 ; $7523 \ DIS ; $7524 | MVI@ R4, R5 ; $7525 | DECR R5 ; $7526 |-- Decrement count at $8437. DECR R4 ; $7527 | EIS ; $7528 | !! EIS is non-interruptible! MVO@ R5, R4 ; $7529 / L752A: PULR R5 ; $752A Restore decoded value from stack CLRC ; $752B Clear carry (success) L752C: PULR R4 ; $752C Restore R4 L752D: PULR R7 ; $752D Return. ;;============================================================================= ;; Read and decode a DECLE from FIFO @$8438, blocking. ;;----------------------------------------------------------------------------- L752E: PSHR R5 ; $752E \ L752F: JSR R5, L7502 ; $752F |-- Spin until we read something BC L752F ; $7532 / PULR R7 ; $7534 ;;============================================================================= ;;============================================================================= ;; Flush input FIFO @ $8308, and set up FIFO at $8438. ;;----------------------------------------------------------------------------- L7535: PSHR R5 ; $7535 Save return address PSHR R0 ; $7536 Save R0 SDBD ; $7537 \ MVII #$8437, R5 ; $7538 |__ Clear location $8437 CLRR R0 ; $753B | MVO@ R0, R5 ; $753C / ! DIS ; $753D \ ! MVII #$002D, R0 ; $753E | ! MVO@ R0, R5 ; $7540 | Initialize a $2D-word FIFO ! MVO@ R0, R5 ; $7541 |-- at $8438. Instrs marked (!) ! INCR R0 ; $7542 | are non-interruptible. ! EIS ; $7543 | ! MVO@ R0, R5 ; $7544 / ! SUBI #$0132, R5 ; $7545 \ Make input FIFO @ $8308 empty ! MVI@ R5, R0 ; $7547 |__ by writing tail pointer to SUBI #$0002, R5 ; $7548 | head pointer. MVO@ R0, R5 ; $754A / PULR R0 ; $754B Restore R0 PULR R7 ; $754C Return. ;;============================================================================= PSHR R0 ; $754D 0270 [. ] PSHR R4 ; $754E 0274 [. ] MVI@ R5, R0 ; $754F 02A8 [. ] SDBD ; $7550 0001 [. ] MVI@ R5, R4 ; $7551 02AC [. ] PSHR R5 ; $7552 0275 [. ] JSR R5, L755A ; $7553 0004 0174 015A [...] L7556: PULR R5 ; $7556 02B5 [. ] PULR R4 ; $7557 02B4 [. ] PULR R0 ; $7558 02B0 [. ] MOVR R5, R7 ; $7559 00AF [. ] ;;============================================================================= ;; Copy argument block to RPC6502 command block ;; ;; INPUTS: ;; R0 -- Command number ($01 .. $0C) (if L757F) ;; R4 -- Pointer to 3-byte parameter block ;; R5 -- Return address ;; ;; OUTPUTS: ;; R4 -- Unchanged ;; R5 -- Points to $8302. ;;----------------------------------------------------------------------------- L755A: PSHR R5 ; $755A PSHR R0 ; $755B L755C: SDBD ; $755C \ MVII #$8301, R5 ; $755D | MVI@ R5, R0 ; $7560 |-- Spin until $8301 goes zero TSTR R0 ; $7561 | BNEQ L755C ; $7562 / MVI@ R4, R0 ; $7564 \ MVO@ R0, R5 ; $7565 | MVI@ R4, R0 ; $7566 |__ Blast a 3-byte message to MVO@ R0, R5 ; $7567 | $8302 - $8304. MVI@ R4, R0 ; $7568 | MVO@ R0, R5 ; $7569 / SUBI #$0004, R5 ; $756A Rewind R5 back to $8301 PULR R0 ; $756C \___ Store our RPC command number MVO@ R0, R5 ; $756D / SUBI #$0003, R4 ; $756E Rewind R4. PULR R7 ; $7570 Return. ;;============================================================================= ;;============================================================================= ;; Invoke a command on the 6502 side and return the result. ;; ;; INPUTS for L7571 ;; R5 -- Pointer three decles of parameters. Function returns after ;; parameters. ;; RPC Command Number 1 DECLE ;; Ptr to paramter block 2 DECLES (in BIDECLE format) ;; ;; INPUTS for L757C ;; R4 -- Pointer to parameter block. ;; R5 -- Pointer to RPC Command Number. Function returns after this decle. ;; ;; INPUTS for L757F ;; R0 -- RPC Command number ($01 .. $0C) ;; R4 -- Pointer to 3-byte parameter block ;; R5 -- Return address. ;; ;; For all inputs, the RPC command number is a value between $01 and $0C ;; (inclusive) that requests some action from the 6502-side of things. ;; The 3-byte parameter block acts as arguments to this RPC call. These ;; bytes form "Arg1", "Arg2", and "Arg3", respectively, and their meaning ;; varies according to the RPC command number. ;; ;; OUTPUTS: ;; R0,R1,R2,R3,R4 -- Unchanged ;; R5 -- Points to return address ;; C -- Set if error, Clear if ok. ;;----------------------------------------------------------------------------- L7571: PSHR R0 ; $7571 Save R0 PSHR R4 ; $7572 Save R4 MVI@ R5, R0 ; $7573 Get RPC cmd number from SDBD ; $7574 \___ Get the pointer to the parameter MVI@ R5, R4 ; $7575 / block. PSHR R5 ; $7576 Save our return address JSR R5, L757F ; $7577 Do RPC command B L7556 ; $757A Restore R5, R4, R0 and return. L757C: PSHR R0 ; $757C Save R0 MVI@ R5, R0 ; $757D Get arg from after JSR INCR R7 ; $757E skip next instruction L757F: PSHR R0 ; $757F Save R0 PSHR R5 ; $7580 Save return address JSR R5, L755A ; $7581 Go blast 3-byte record to 6502 L7584: DECR R5 ; $7584 \ MVI@ R5, R0 ; $7585 |__ Spin until $8301 goes zero TSTR R0 ; $7586 | again (meaning 6502 done). BNEQ L7584 ; $7587 / SUBI #$0002, R5 ; $7589 Point to $8300 -- return code XOR@ R5, R0 ; $758B Was it zero? CLRC ; $758C \___ Yes: Return w/ carry clear BEQ L7590 ; $758D / SETC ; $758F No: Return w/ carry set. L7590: PULR R5 ; $7590 \___ restore saved R5, R0 PULR R0 ; $7591 / MOVR R5, R7 ; $7592 Return. ;;============================================================================= ;;============================================================================= ;; RPC cmd #1 to 6502, arg in @R5 ;;----------------------------------------------------------------------------- L7593: PSHR R4 ; $7593 Save R4. MOVR R5, R4 ; $7594 Point to arg after JSR INCR R5 ; $7595 Fix return address B L759F ; $7596 Go do RPC command ;;============================================================================= ;; RPC cmd #1 to 6502, arg in R1 ;;----------------------------------------------------------------------------- L7598: PSHR R4 ; $7598 Save arg block pointer SDBD ; $7599 \ MVII #$83C0, R4 ; $759A |-- Save argument to $83C0 block MVO@ R1, R4 ; $759D / DECR R4 ; $759E Point R4 back at $83C0 ; fall-thru ;;============================================================================= ;; RPC cmd #1 to 6502, arg @R4 ;;----------------------------------------------------------------------------- L759F: PSHR R5 ; $759F Save return address JSR R5, L757C ; $75A0 \___ RPC cmd #1 DECLE $001 ; / SDBD MVII #$8305, R5 ; $75A5 \___ Get return value from RPC call MVI@ R5, R0 ; $75A8 / into R0. ; fall-thru ;;============================================================================= ;; Restore R4, R5 from stack and return to R5. ;;----------------------------------------------------------------------------- L75A9: PULR R5 ; $75A9 Pop R5 PULR R4 ; $75AA Pop R4 MOVR R5, R7 ; $75AB Return to R5 ;;============================================================================= ;;============================================================================= ;; RPC cmd #2 to 6502 side. Consumes two decles after JSR as arguments. ;;----------------------------------------------------------------------------- L75AC: PSHR R4 ; $75AC 0274 [. ] MOVR R5, R4 ; $75AD 00AC [. ] ADDI #$0002, R5 ; $75AE 02FD 0002 [.. ] B L75BB ; $75B0 0200 0009 [.. ] ;;============================================================================= ;; RPC cmd #2 to 6502 side. Arguments come in R0, R1 ;;----------------------------------------------------------------------------- L75B2: PSHR R4 ; $75B2 Save R4 on stack. SDBD ; $75B3 \ MVII #$83C0, R4 ; $75B4 | MVO@ R1, R4 ; $75B7 |-- Save two args @$83C0 and MVO@ R0, R4 ; $75B8 | leave R4 -> $83C0 SUBI #$0002, R4 ; $75B9 / L75BB: PSHR R5 ; $75BB JSR R5, L757C ; $75BC \___ RPC call to 6502, cmd #2. DECLE $002 ; / B L75A9 ; $75C0 0220 0018 [.. ] ;;============================================================================= ;; RPC cmd #3 to 6502 side. Consumes two decles after JSR as arguments. ;; Returns result value in R0. ;;----------------------------------------------------------------------------- L75C2: PSHR R4 ; $75C2 Save R4 on stack MOVR R5, R4 ; $75C3 Use R5 as arg ptr for RPC call below ADDI #$0002, R5 ; $75C4 Make R5 proper return address. B L75D1 ; $75C6 Dispatch RPC call. ;;============================================================================= ;; RPC cmd #3 to 6502 side. Arguments come in R0, R1. ;; Returns result value in R0. ;;----------------------------------------------------------------------------- L75C8: PSHR R4 ; $75C8 Save R4 on stack SDBD ; $75C9 \ MVII #$83C0, R4 ; $75CA | MVO@ R1, R4 ; $75CD |-- Save two args @$83C0 and MVO@ R0, R4 ; $75CE | leave R4 -> $83C0 SUBI #$0002, R4 ; $75CF / L75D1: PSHR R5 ; $75D1 Save return address. JSR R5, L757C ; $75D2 \___ RPC call to 6502, cmd #3. DECLE $003, $001 ; / MVII #$8305, R5 ; $75D7 \ Read decle from input FIFO MVI@ R5, R0 ; $75DA |-- and return to the caller. B L75A9 ; $75DB / Return restores R4, R5. ;;============================================================================= PSHR R4 ; $75DD 0274 [. ] MOVR R5, R4 ; $75DE 00AC [. ] ADDI #$0003, R5 ; $75DF 02FD 0003 [.. ] B L75ED ; $75E1 0200 000A [.. ] ;;============================================================================= ;; ? ;;----------------------------------------------------------------------------- L75E3: PSHR R4 ; $75E3 Save prev caller's return address SDBD ; $75E4 \ MVII #$83C0, R4 ; $75E5 | Save 1st, 2nd, and 4th argument MVO@ R1, R4 ; $75E8 |-- to $83C0..$83C2 MVO@ R0, R4 ; $75E9 | MVO@ R2, R4 ; $75EA / SUBI #$0003, R4 ; $75EB Point R4 back at $83C0 L75ED: PSHR R5 ; $75ED JSR R5, L757C ; $75EE DECLE $004 ; $75F1 B L763E ; $75F2 Return to caller. ;;============================================================================= ;; Copy a block of data to 6502 side via RPC cmd #4 ;; [POKE PEEK($340 + 12 * Arg1 + 6) + Arg2, Arg3] ;; ;; INPUTS: ;; R5 -- Extended of RPC record to execute ;; Arg 1 (Remains fixed) ;; Arg 2 (Increments during loop) ;; Count ;; Bytes to store ("Count" bytes long) ;; ;; OUTPUTS: ;; All regs trashed? ;;----------------------------------------------------------------------------- L75F4: MOVR R5, R4 ; $75F4 \ MVI@ R4, R1 ; $75F5 | MVI@ R4, R0 ; $75F6 |-- Grab 4 args from after call site MVI@ R4, R3 ; $75F7 | L75F8: MVI@ R4, R2 ; $75F8 / JSR R5, L75E3 ; $75F9 \ INCR R0 ; $75FC |__ Loop around 3rd_arg times. DECR R3 ; $75FD | BNEQ L75F8 ; $75FE / MOVR R4, R7 ; $7600 Return. ;;============================================================================= ;;============================================================================= ;; RPC cmd #6. 1 arg after JSR, 1 arg in R1. ;;----------------------------------------------------------------------------- L7601: PSHR R0 ; $7601 Save R0 MVI@ R5, R0 ; $7602 Get argument after JSR INCR R7 ; $7603 Skip "PSHR R0" (Branch to L7605) ; fall-thru ;;============================================================================= ;; RPC cmd #6, 2 args in R0, R1. ;;----------------------------------------------------------------------------- L7604: PSHR R0 ; $7604 Save R0 L7605: PSHR R5 ; $7605 Save return address CMPI #$0004, R0 ; $7606 \__ If arg <= 4, skip next call BLE L760D ; $7608 / JSR R5, L7671 ; $760A Spin until RPC cmd #1, arg 1 ; returns w/ bit 7 == 0. L760D: PSHR R4 ; $760D Save R4 SDBD ; $760E \ MVII #$83C0, R4 ; $760F | MVO@ R0, R4 ; $7612 | Save decle from R0 and bidecle MVO@ R1, R4 ; $7613 |-- from R1 into argument block at SWAP R1 ; $7614 | $83C0 MVO@ R1, R4 ; $7615 | SWAP R1 ; $7616 / SUBI #$0003, R4 ; $7617 Rewind to $83C0 JSR R5, L757C ; $7619 RPC command #6. DECLE $006 ; PULR R4 ; $761D Restore R4 PULR R5 ; $761E Restore R5 PULR R0 ; $761F Restore R0 MOVR R5, R7 ; $7620 Return ;;============================================================================= ;;============================================================================= ;; Synchronize w/ 6502 side via semaphore at $8306. ;; We wait for 4 sync events from 6502 side. ;;----------------------------------------------------------------------------- L7621: PSHR R5 ; $7621 Save return address. MVII #$0003, R0 ; $7622 Start by writing 3. L7624: SDBD ; $7624 \ MVII #$8306, R5 ; $7625 | MVO@ R0, R5 ; $7628 | L7629: DECR R5 ; $7629 | Wait for $000x to become MVI@ R5, R2 ; $762A |-- $0x0x. This happens w/ PSHR R2 ; $762B | "LDA $0306; STA $4306" on 6502. SWAP R2 ; $762C | XOR@ R6, R2 ; $762D | BNEQ L7629 ; $762E / DECR R0 ; $7630 \ Loop through 2, 1, 0 BPL L7624 ; $7631 / PULR R7 ; $7633 Return. ;;============================================================================= ;;============================================================================= ;; Signal to 6502 that we're DONE sending a message. Set $83DA to #$FF ;;----------------------------------------------------------------------------- L7634: MVII #$00FF, R0 ; $7634 Prepare to set $83DA to #$00FF INCR R7 ; $7636 Skip the CLRR R0. ;fall thru to L7638 ;;============================================================================= ;; Signal to 6502 that we're sending a message. Set $83DA to #$00 ;;----------------------------------------------------------------------------- L7637: CLRR R0 ; $7637 Prepare to set $83DA to #$00FF ;;============================================================================= ;; Set $83DA to R0. ;;----------------------------------------------------------------------------- L7638: PSHR R5 ; $7638 Save return address SDBD ; $7639 \ MVII #$83DA, R5 ; $763A |-- Set $83DA to value in R0 MVO@ R0, R5 ; $763D / L763E: PULR R7 ; $763E Return. ;;============================================================================= ;;============================================================================= ;; RESET 6502 side and have it vector to address passed after JSR. ;;----------------------------------------------------------------------------- L763F: PSHR R4 ; $763F Save R4 MOVR R5, R4 ; $7640 Point R4 at argument after JSR JSR R5, L757C ; $7641 \___ RPC command #A, using caller's DECLE $00A ; $7644 / argument as arg to RPC. MOVR R4, R5 ; $7645 \___ Point R5 at proper return addr. ADDI #$0002, R5 ; $7646 / PULR R4 ; $7648 Restore R4 MOVR R5, R7 ; $7649 Return ;;============================================================================= ;;============================================================================= ;; ?TAPE? command ;;----------------------------------------------------------------------------- L764A: PSHR R1 ; $764A 0271 [. ] SDBD ; $764B 0001 [. ] MVII #$84E4, R1 ; $764C 02B9 00E4 0084 [...] B L765E ; $764F 0200 000D [.. ] ;;============================================================================= ;; ?TAPE? command ;;----------------------------------------------------------------------------- L7651: PSHR R1 ; $7651 0271 [. ] SDBD ; $7652 0001 [. ] XORI #$8000, R1 ; $7653 03F9 0000 0080 [...] INCR R7 ; $7656 000F [. ] ; fallthru to $7658 ;;============================================================================= ;; ?TAPE? command ;;----------------------------------------------------------------------------- L7657: PSHR R1 ; $7657 0271 [. ] SDBD ; $7658 0001 [. ] XORI #$4000, R1 ; $7659 03F9 0000 0040 [..@] INCR R7 ; $765C 000F [. ] ; fallthru to $765E ;;============================================================================= ;; ?TAPE? command ;;----------------------------------------------------------------------------- L765D: PSHR R1 ; $765D 0271 [. ] L765E: PSHR R5 ; $765E 0275 [. ] JSR R5, L7601 ; $765F 0004 0174 0201 [...] DECLE $003 ; RPC cmd #6, Arg $003. PULR R5 ; $7663 02B5 [. ] PULR R1 ; $7664 02B1 [. ] MOVR R5, R7 ; $7665 00AF [. ] ;;============================================================================= ;;============================================================================= ;; Poll location $34C on 6502 via RPC, and AND w/DECLE after JSR to set Z bit. ;;----------------------------------------------------------------------------- L7666: PSHR R0 ; $7666 Save R0. PSHR R5 ; $7667 Save arg addr JSR R5, L7593 ; $7668 \___ RPC cmd #1, arg = $001 DECLE $001 ; / ==> PEEK($34C) PULR R5 ; $766C Get arg addr AND@ R5, R0 ; $766D Set "Z" based on R0 AND RPC rtn val PULR R0 ; $766E Restore R0 PSHR R5 ; $766F \___ Return w/out destroying flags. PULR R7 ; $7670 / ;;============================================================================= ;;============================================================================= ;; Spin until location $34C on 6502 returns bit 7 == 0. (via RPC) ;; Poll $34C once more and return bit 5 in Carry. (again via RPC) ;;----------------------------------------------------------------------------- L7671: PSHR R5 ; $7671 Save return address L7672: JSR R5, L7666 ; $7672 \ DECLE $80 ; $7675 |-- Wait for RPC #1 to return with BNEQ L7672 ; $7676 / bit 7 clear. INCR R7 ; $7678 Skip the PSHR R5 ; fall-thru ;;============================================================================= ;; Poll $34C on 6502 via RPC. Return w/ C == bit 5 of result. ;;----------------------------------------------------------------------------- L7679: PSHR R5 ; $7679 Save return address JSR R5, L7666 ; $767A \___ Poll $34C and test bit 5 DECLE $20 ; / CLRC ; $767E BEQ L7682 ; $767F Not set: Return w/ C==0 SETC ; $7681 Is set: Return w/ C==1 L7682: PULR R7 ; $7682 Return. ;;============================================================================= ;;============================================================================= ;; ?TAPE? command ;;----------------------------------------------------------------------------- L7683: PSHR R5 ; $7683 JSR R5, L7666 ; $7684 Poll $34C via RPC and test bit 1 DECLE $002 ; BNEQ L7682 ; $7688 Set? Return. JSR R5, L73D0 ; $768A 0004 0170 03D0 [...] ;------ "\r\n Rewinding...\r\n", 0 DECLE $301, $104 ; "\r\n", cursor to col 4. DECLE $343, $324 ; "Rewinding" DECLE $30B, $301, 0 ; "...\r\n", 0 INCR R7 ; $7694 000F [. ] ; fall thru to 7696 ;;============================================================================= ;; ?TAPE? command ;;----------------------------------------------------------------------------- L7695: PSHR R5 ; $7695 0275 [. ] L7696: JSR R5, L7601 ; $7696 0004 0174 0201 [...] DECLE $00A ; RPC cmd #6, Arg $00A. B L7672 ; $769A 0220 0029 [.) ] ;;============================================================================= ;;============================================================================= ;; ?TAPE? command ;;----------------------------------------------------------------------------- L769C: PSHR R5 ; $769C 0275 [. ] L769D: JSR R5, L7601 ; $769D 0004 0174 0201 [...] DECLE $009 ; RPC cmd #6, Arg $009. B L7672 ; $76A1 0220 0030 [.0 ] ;;============================================================================= ;;============================================================================= ;; Start recording a cassette if requested by 6502??? ;;----------------------------------------------------------------------------- L76A3: PSHR R5 ; $76A3 Save return addrress. JSR R5, L7666 ; $76A4 \___ Poll tape status at $34C on 6502 DECLE $80 ; $76A7 / in bit 7. BEQ L7682 ; $76A8 If bit 7 was clear, return. JSR R5, L7601 ; $76AA RPC cmd #6. Arg $004. DECLE $004 ; BNC L7672 ; $76AE If C==0, spin until RPC cmd #1 arg 1 ; returns bit 7 clear, and then ; RPC cmd 1 arg 1 again return with ; C = bit 5 of the result. ; (Wait until tape is stopped if ; user cancels recording or tape is ; write protected?) JSR R5, L73DB ; $76B0 Display a character to the 6502 DECLE $0302 ; "(Recording)\r\n\t" JSR R5, L7601 ; $76B4 RPC cmd #6 arg $004 DECLE $0004 ; BC L76B4 ; $76B8 Spin until carry is set. ; (Wait until recording is stopped?) B L7672 ; $76BA Spin until RPC cmd #1 arg 1 returns ; bit 7 clear, and then do RPC cmd #1 ; arg 1 again and return with carry = ; bit 5 of the result. ; (Wait until tape is stopped?) ;;============================================================================= ;;============================================================================= ;; ?TAPE? command ;;----------------------------------------------------------------------------- L76BC: PSHR R5 ; $76BC 0275 [. ] JSR R5, L7601 ; $76BD 0004 0174 0201 [...] DECLE $00D ; RPC cmd #6, Arg $00D. B L7672 ; $76C1 0220 0050 [.P ] ;;============================================================================= ;;============================================================================= ;; Save tons of context to $8482 .. $84DF. ;; Temporarily saves/restores stack frame as part of this. ;; Stuff at $84BF-$84DF is the important stuff. $8482-$84BE is available ;; after this routine is done. ;;----------------------------------------------------------------------------- L76C3: MOVR R6, R0 ; $76C3 Save current stack pointer in R0 PSHR R5 ; $76C4 Remember return address on stack. MVII #$001F, R2 ; $76C5 \ SDBD ; $76C7 |__ Save 30 words of stack and MVII #$8482, R5 ; $76C8 | SP itself to $8482..$84BE MVII #$02F1, R4 ; $76CB / B L76D2 ; $76CD First iter: Save stack ptr itself L76CF: MVI@ R4, R0 ; $76CF \ MVO@ R0, R5 ; $76D0 | SWAP R0 ; $76D1 |__ Roll out the stack frame to L76D2: MVO@ R0, R5 ; $76D2 | $8482 and up. DECR R2 ; $76D3 | BNEQ L76CF ; $76D4 / MOVR R5, R1 ; $76D6 Save "save-area" ptr in R1. PULR R5 ; $76D7 Get our return address. MVII #$02F1, R6 ; $76D8 Reset stack. PSHR R5 ; $76DA Push our return address on new stack. JSR R5, L7114 ; $76DB Make L7710 current ISR. BIDECLE L7710, $0100 ; (Store L7710 -> $0100 vector.) MOVR R1, R4 ; $76E2 \___ R1 == $84BF SUBI #$0053, R4 ; $76E3 / R4 == $846C MVII #$000F, R0 ; $76E5 \___ Copy 15 words from $846C to JSR R5, G1730 ; $76E7 / $84BF MOVR R5, R4 ; $76EA R5 points to $84CE. Save it. JSR R5, L75C2 ; $76EB Get ?? from 6502 via RPC cmd #3 DECLE $01, $02 ; This works out to ($352),2. ; By dflt, this is $00CB on 6502-side. MVO@ R0, R4 ; $76F0 Store it at $84CE. JSR R5, L75C2 ; $76F1 Get ?? from 6502 via RPC cmd #3 DECLE $01, $03 ; This works out to ($352),3. ; By dflt, this is $00CC on 6502-side. MVO@ R0, R4 ; $76F6 Store it at $84CF. MOVR R4, R1 ; $76F7 \___ R4 == $84D0 SUBI #$0190, R1 ; $76F8 / R1 == $8340 MVI@ R1, R0 ; $76FA \___ Save display flags from $8340 MVO@ R0, R4 ; $76FB / to $84D0. MVI $0149, R0 ; $76FC \___ Save $0149 (?sound type) to $84D1 MVO@ R0, R4 ; $76FE / MOVR R4, R1 ; $76FF \ MVII #$01F0, R4 ; $7700 |__ Save PSG state to $84D2..$84DF MVII #$000E, R0 ; $7702 | JSR R5, G1730 ; $7704 / JSR R5, L711C ; $7707 \ DECLE $001 ; |-- Set bit 1 at $8480 BIDECLE $8480 ; / PULR R5 ; $770D Restore return address in R5. B L7768 ; $770E 0200 0058 [.X ] ;;============================================================================= ;;============================================================================= ;; ISR: Save current screen color in $83FF, chain to normal ISR handler. ;;----------------------------------------------------------------------------- L7710: MVII #$002C, R3 ; $7710 \ SDBD ; $7712 | MVII #$83FF, R5 ; $7713 |-- Save current screen color in MVI@ R3, R0 ; $7716 | $83FF. MVO@ R0, R5 ; $7717 / J L712E ; $7718 Chain to default ISR handler ;;============================================================================= ;;============================================================================= ;; Strobe STIC Display Enable ;;----------------------------------------------------------------------------- L771B MVII #$0020, R3 ; $771B \ MVO@ R0, R3 ; $771D |-- Why not just "MVO R0, $0020"? MOVR R5, R7 ; $771E / ;;============================================================================= ;;============================================================================= ;; Get saved screen color from $83FF, and write it to STIC bg color. ;;----------------------------------------------------------------------------- L771F: SDBD ; $771F \ MVII #$83FF, R4 ; $7720 |-- Get saved color from loc $83FF MVI@ R4, R0 ; $7723 / B L7728 ; $7724 Write R0 to STIC background color ;;============================================================================= ;;============================================================================= ;; ISR: Make display green. (Initial powerup ISR.) ;;----------------------------------------------------------------------------- L7726: MVII #$0005, R0 ; $7726 \ L7728: MVII #$002C, R3 ; $7728 |__ Make display green. MVO@ R0, R3 ; $772A | MOVR R5, R7 ; $772B / ;;============================================================================= L772C: PSHR R5 ; $772C JSR R5, L7114 ; $772D BIDECLE L7726, $0100 ; Make L7726 new ISR. SDBD ; $7734 0001 [. ] MVII #$84BF, R4 ; $7735 02BC 00BF 0084 [...] MOVR R4, R1 ; $7738 00A1 [. ] SUBI #$0053, R1 ; $7739 0339 0053 [.S ] MVII #$000F, R0 ; $773B 02B8 000F [.. ] JSR R5, G1730 ; $773D 0004 0114 0330 [...] SDBD ; $7740 0001 [. ] MVI@ R4, R1 ; $7741 02A1 [. ] MOVR R4, R5 ; $7742 00A5 [. ] SUBI #$0050, R5 ; $7743 033D 0050 [.P ] MVI@ R5, R5 ; $7745 02AD [. ] ANDI #$0100, R5 ; $7746 03BD 0100 [.. ] BEQ L774D ; $7748 0204 0003 [.. ] JSR R5, L76BC ; $774A 0004 0174 02BC [...] L774D: MVI@ R4, R0 ; $774D 02A0 [. ] MOVR R4, R1 ; $774E 00A1 [. ] SUBI #$0191, R1 ; $774F 0339 0191 [.. ] MVO@ R0, R1 ; $7751 0248 [. ] MVI@ R4, R0 ; $7752 02A0 [. ] TSTR R0 ; $7753 0080 [. ] BEQ L775D ; $7754 0204 0007 [.. ] MVII #$01F0, R1 ; $7756 02B9 01F0 [.. ] MVII #$000E, R0 ; $7758 02B8 000E [.. ] JSR R5, G1730 ; $775A 0004 0114 0330 [...] L775D: JSR R5, L7114 ; $775D 0004 0170 0114 [...] COMR R7 ; $7760 001F [. ] RRC R3, 2 ; $7761 0077 [w ] HLT ; $7762 0000 [. ] SDBD ; $7763 0001 [. ] JSR R5, L7621 ; $7764 0004 0174 0221 [...] PULR R5 ; $7767 02B5 [. ] ;;============================================================================= ;; Restore stack frame at $8482 back to stack. ;;----------------------------------------------------------------------------- L7768: MVII #$02F1, R6 ; $7768 Point to start of stack SDBD ; $776A \ MVII #$8482, R4 ; $776B |__ Point at stack save area. MVI@ R4, R3 ; $776E | Get old stack pointer. MVII #$001E, R1 ; $776F / DIS ; $7771 \ L7772: SDBD ; $7772 | MVI@ R4, R0 ; $7773 | PSHR R0 ; $7774 |__ Copy the stack frame back DECR R1 ; $7775 | BNEQ L7772 ; $7776 | EIS ; $7778 | NOTE! EIS is non-interruptible. MOVR R3, R6 ; $7779 / Restore stack pointer ;fall-thru ;;============================================================================= ;; Make L712E the current ISR. ;;----------------------------------------------------------------------------- L777A: MVII #$0100, R4 ; $777A \ MVII #$002E, R0 ; $777C | MVII #$0071, R1 ; $777E |-- Make L712E the current ISR. MVO@ R0, R4 ; $7780 | MVO@ R1, R4 ; $7781 / MOVR R5, R7 ; $7782 Return ;;============================================================================= ;;============================================================================= ;; Read DECLE from FIFO, return C==1 if empty. ;;----------------------------------------------------------------------------- L7783: PSHR R2 ; $7783 Save R2 MVI@ R4, R2 ; $7784 \ CMP@ R4, R2 ; $7785 |-- Does head == tail? If so, BEQ L7798 ; $7786 / return C==1. INCR R2 ; $7788 \ CMP@ R4, R2 ; $7789 |__ Increment head ptr modulo FIFO BMI L778E ; $778A | size. MVII #$0003, R2 ; $778C / L778E: SUBI #$0003, R4 ; $778E ADDR R4, R2 ; $7790 Move R2 to point directly in FIFO. MVI@ R2, R0 ; $7791 Get DECLE from FIFO. SUBR R4, R2 ; $7792 Make R2 tail pointer again. MVO@ R2, R4 ; $7793 Store new head pointer. DECR R4 ; $7794 Restore R4 PULR R2 ; $7795 Restore R2 CLRC ; $7796 Clear carry (success) MOVR R5, R7 ; $7797 Return L7798: SUBI #$0002, R4 ; $7798 Restore R4 CLRR R0 ; $779A Return NUL as our character B L77BA ; $779B Restore R2, Set carry (error), Return ;;============================================================================= ;; Enqueue a DECLE from R0 in FIFO pointed to by R4. ;; Returns C=0 on success ;;----------------------------------------------------------------------------- L779D: PSHR R2 ; $779D Save R2 PSHR R1 ; $779E Save R1 MVI@ R4, R2 ; $779F Get head pointer MVI@ R4, R1 ; $77A0 Get tail pointer INCR R1 ; $77A1 \ CMP@ R4, R1 ; $77A2 |__ Advance tail modulo FIFO size BMI L77A7 ; $77A3 | MVII #$0003, R1 ; $77A5 / L77A7: CMPR R2, R1 ; $77A7 Tail == head? BEQ L77B7 ; $77A8 Yes: Full. Return Error SUBI #$0003, R4 ; $77AA \ ADDR R4, R1 ; $77AC |-- Store decle at tail of FIFO MVO@ R0, R1 ; $77AD / SUBR R4, R1 ; $77AE \ INCR R4 ; $77AF |-- Store new tail pointer. MVO@ R1, R4 ; $77B0 / SUBI #$0002, R4 ; $77B1 Restore FIFO pointer PULR R1 ; $77B3 Restore R1 PULR R2 ; $77B4 Restore R2 CLRC ; $77B5 C==0 (success) MOVR R5, R7 ; $77B6 Return L77B7: SUBI #$0003, R4 ; $77B7 Restore FIFO pointer PULR R1 ; $77B9 Restore R1 L77BA: PULR R2 ; $77BA Restore R2 SETC ; $77BB C==1 (FIFO full) MOVR R5, R7 ; $77BC Return. ;;============================================================================= ;;============================================================================= ;; Lookup Table pointed to by $8470 ;;----------------------------------------------------------------------------- L77BD: DECLE $042, $062, $062, $042, $002, $041, $001, $042 DECLE $042, $042, $042, $042, $042, $062, $042, $042 DECLE $000, $000, $000, $000, $000, $000, $000, $000 DECLE $084, $084, $084, $084, $084, $000, $000, $000 DECLE $108, $108, $108, $108, $108, $108, $108, $108 DECLE $108, $108, $108, $108, $108, $008, $000, $000 DECLE $200, $210, $210, $210, $210, $210, $210, $210 DECLE $210, $210, $210, $210, $210, $210, $010, $000 ;;============================================================================= CMPR R6, R3 ; $77FD 0173 [. ] CMPR R4, R5 ; $77FE 0165 [. ] NEGR R0 ; $77FF 0020 [ ] MVII #$0002, R0 ; $7800 02B8 0002 [.. ] SUBI #$0010, R2 ; $7802 033A 0010 [.. ] MVO@ R0, R2 ; $7804 0250 [. ] MVII #$0007, R0 ; $7805 02B8 0007 [.. ] MVO@ R0, R3 ; $7807 0258 [. ] L7808: DECR R6 ; $7808 0016 [. ] MVII #$035C, R2 ; $7809 02BA 035C [.. ] L780B: MVI@ R2, R1 ; $780B 0291 [. ] ADDI #$0101, R1 ; $780C 02F9 0101 [.. ] MVI@ R1, R3 ; $780E 028B [. ] MOVR R3, R5 ; $780F 009D [. ] ADDR R3, R5 ; $7810 00DD [. ] ADDR R3, R5 ; $7811 00DD [. ] ADD@ R2, R5 ; $7812 02D5 [. ] ADDI #$0099, R5 ; $7813 02FD 0099 [.. ] MOVR R4, R0 ; $7815 00A0 [. ] MVO@ R0, R5 ; $7816 0268 [. ] SWAP R0 ; $7817 0040 [@ ] MVO@ R0, R5 ; $7818 0268 [. ] INCR R5 ; $7819 000D [. ] PULR R7 ; $781A 02B7 [. ] MOVR R3, R5 ; $781B 009D [. ] DECR R1 ; $781C 0011 [. ] BPL L7820 ; $781D 0203 0001 [.. ] MVI@ R3, R1 ; $781F 0299 [. ] L7820: SDBD ; $7820 0001 [. ] MVI@ R4, R0 ; $7821 02A0 [. ] CMP@ R3, R1 ; $7822 0359 [. ] BNEQ L7827 ; $7823 020C 0002 [.. ] MOVR R0, R4 ; $7825 0084 [. ] PULR R7 ; $7826 02B7 [. ] L7827: ADDR R1, R5 ; $7827 00CD [. ] ADDR R1, R5 ; $7828 00CD [. ] ADDR R1, R5 ; $7829 00CD [. ] SUBI #$0068, R5 ; $782A 033D 0068 [.h ] B L7984 ; $782C 0200 0156 [.. ] MVI@ R4, R0 ; $782E 02A0 [. ] DECR R1 ; $782F 0011 [. ] BPL L7833 ; $7830 0203 0001 [.. ] L7832: MVI@ R3, R1 ; $7832 0299 [. ] L7833: MOVR R1, R5 ; $7833 008D [. ] ADDR R1, R5 ; $7834 00CD [. ] ADDR R1, R5 ; $7835 00CD [. ] ADDR R3, R5 ; $7836 00DD [. ] SUBI #$0066, R5 ; $7837 033D 0066 [.f ] MVO@ R0, R5 ; $7839 0268 [. ] B L7852 ; $783A 0200 0016 [.. ] MVII #$0200, R0 ; $783C 02B8 0200 [.. ] INCR R7 ; $783E 000F [. ] CLRR R0 ; $783F 01C0 [. ] DECR R1 ; $7840 0011 [. ] BPL L7844 ; $7841 0203 0001 [.. ] MVI@ R3, R1 ; $7843 0299 [. ] L7844: MOVR R1, R2 ; $7844 008A [. ] ADDR R1, R2 ; $7845 00CA [. ] ADDR R1, R2 ; $7846 00CA [. ] ADDR R3, R2 ; $7847 00DA [. ] SUBI #$0066, R2 ; $7848 033A 0066 [.f ] MVI@ R2, R5 ; $784A 0295 [. ] ANDI #$01FF, R5 ; $784B 03BD 01FF [.. ] XORR R0, R5 ; $784D 01C5 [. ] MVO@ R5, R2 ; $784E 0255 [. ] TSTR R0 ; $784F 0080 [. ] BEQ L78D4 ; $7850 0204 0082 [.. ] L7852: CMP@ R3, R1 ; $7852 0359 [. ] BEQ L7808 ; $7853 0224 004C [.L ] PULR R7 ; $7855 02B7 [. ] SDBD ; $7856 0001 [. ] MVI@ R4, R5 ; $7857 02A5 [. ] INCR R5 ; $7858 000D [. ] MVI@ R5, R0 ; $7859 02A8 [. ] JSR R5, G1745 ; $785A 0004 0114 0345 [...] MOVR R3, R2 ; $785D 009A [. ] ADDI #$0002, R2 ; $785E 02FA 0002 [.. ] AND@ R2, R0 ; $7860 0390 [. ] BNEQ L78D4 ; $7861 020C 0071 [.q ] SUBI #$0003, R4 ; $7863 033C 0003 [.. ] INCR R0 ; $7865 0008 [. ] B L7832 ; $7866 0220 0035 [.5 ] CLRR R1 ; $7868 01C9 [. ] JSR R5, L78C4 ; $7869 0004 0178 00C4 [...] PSHR R5 ; $786C 0275 [. ] SDBD ; $786D 0001 [. ] MVI@ R5, R0 ; $786E 02A8 [. ] SDBD ; $786F 0001 [. ] MVI@ R5, R1 ; $7870 02A9 [. ] SDBD ; $7871 0001 [. ] MVI@ R5, R2 ; $7872 02AA [. ] SDBD ; $7873 0001 [. ] MVI@ R5, R3 ; $7874 02AB [. ] MOVR R4, R7 ; $7875 00A7 [. ] PULR R5 ; $7876 02B5 [. ] MVO@ R0, R5 ; $7877 0268 [. ] SWAP R0 ; $7878 0040 [@ ] MVO@ R0, R5 ; $7879 0268 [. ] MVO@ R1, R5 ; $787A 0269 [. ] NOP ; $787B 0034 [4 ] SWAP R1 ; $787C 0041 [A ] MVO@ R1, R5 ; $787D 0269 [. ] MVO@ R2, R5 ; $787E 026A [. ] SWAP R2 ; $787F 0042 [B ] MVO@ R2, R5 ; $7880 026A [. ] MOVR R3, R0 ; $7881 0098 [. ] B L7984 ; $7882 0200 0100 [.. ] DECR R6 ; $7884 0016 [. ] PULR R7 ; $7885 02B7 [. ] MVII #$0001, R3 ; $7886 02BB 0001 [.. ] INCR R7 ; $7888 000F [. ] CLRR R3 ; $7889 01DB [. ] JSR R5, L789D ; $788A 0004 0178 009D [...] SDBD ; $788D 0001 [. ] ADD@ R4, R3 ; $788E 02E3 [. ] MVO@ R1, R3 ; $788F 0259 [. ] PULR R7 ; $7890 02B7 [. ] JSR R5, L789B ; $7891 0004 0178 009B [...] SDBD ; $7894 0001 [. ] MVI@ R4, R5 ; $7895 02A5 [. ] ADDI #$0002, R5 ; $7896 02FD 0002 [.. ] MOVR R1, R0 ; $7898 0088 [. ] B L7984 ; $7899 0200 00E9 [.. ] L789B: MOVR R7, R0 ; $789B 00B8 [. ] INCR R7 ; $789C 000F [. ] L789D: CLRR R0 ; $789D 01C0 [. ] PSHR R5 ; $789E 0275 [. ] MOVR R1, R2 ; $789F 008A [. ] BNEQ L78AA ; $78A0 020C 0008 [.. ] MVI@ R4, R1 ; $78A2 02A1 [. ] TSTR R0 ; $78A3 0080 [. ] BEQ L78D4 ; $78A4 0204 002E [.. ] DECR R4 ; $78A6 0014 [. ] SDBD ; $78A7 0001 [. ] MVI@ R4, R1 ; $78A8 02A1 [. ] PULR R7 ; $78A9 02B7 [. ] L78AA: ANDI #$0003, R1 ; $78AA 03B9 0003 [.. ] JSR R5, L78C4 ; $78AC 0004 0178 00C4 [...] SDBD ; $78AF 0001 [. ] MVI@ R5, R1 ; $78B0 02A9 [. ] SLR R2, 2 ; $78B1 0066 [f ] BNEQ L78D4 ; $78B2 020C 0020 [. ] MOVR R1, R5 ; $78B4 008D [. ] MVI@ R1, R1 ; $78B5 0289 [. ] TSTR R0 ; $78B6 0080 [. ] BEQ L78D4 ; $78B7 0204 001B [.. ] SDBD ; $78B9 0001 [. ] MVI@ R5, R1 ; $78BA 02A9 [. ] PULR R7 ; $78BB 02B7 [. ] L78BC: PSHR R5 ; $78BC 0275 [. ] JSR R5, L78C4 ; $78BD 0004 0178 00C4 [...] SDBD ; $78C0 0001 [. ] MVI@ R5, R0 ; $78C1 02A8 [. ] TSTR R0 ; $78C2 0080 [. ] PULR R7 ; $78C3 02B7 [. ] L78C4: PSHR R5 ; $78C4 0275 [. ] MVII #$035C, R5 ; $78C5 02BD 035C [.. ] MVI@ R5, R5 ; $78C7 02AD [. ] PSHR R5 ; $78C8 0275 [. ] ADDI #$0101, R5 ; $78C9 02FD 0101 [.. ] MVI@ R5, R5 ; $78CB 02AD [. ] ADDR R5, R5 ; $78CC 00ED [. ] ADDR R5, R5 ; $78CD 00ED [. ] ADDR R5, R5 ; $78CE 00ED [. ] ADDR R1, R5 ; $78CF 00CD [. ] ADDR R1, R5 ; $78D0 00CD [. ] ADD@ R6, R5 ; $78D1 02F5 [. ] ADDI #$00C1, R5 ; $78D2 02FD 00C1 [.. ] L78D4: PULR R7 ; $78D4 02B7 [. ] SUBI #$0250, R2 ; $78D5 033A 0250 [.. ] MVO@ R1, R2 ; $78D7 0251 [. ] PULR R7 ; $78D8 02B7 [. ] SUBI #$024F, R2 ; $78D9 033A 024F [.. ] MOVR R2, R1 ; $78DB 0091 [. ] MVII #$0004, R0 ; $78DC 02B8 0004 [.. ] L78DE: JSR R5, G1731 ; $78DE 0004 0114 0331 [...] SUBI #$024B, R2 ; $78E1 033A 024B [.. ] MVO@ R1, R2 ; $78E3 0251 [. ] PULR R7 ; $78E4 02B7 [. ] JSR R5, L7918 ; $78E5 0004 0178 0118 [...] MVI@ R4, R0 ; $78E8 02A0 [. ] MVI@ R4, R1 ; $78E9 02A1 [. ] MVI@ R4, R2 ; $78EA 02A2 [. ] MVI@ R4, R3 ; $78EB 02A3 [. ] PSHR R4 ; $78EC 0274 [. ] MVI@ R4, R4 ; $78ED 02A4 [. ] L78EE: PSHR R0 ; $78EE 0270 [. ] L78EF: MVO@ R2, R5 ; $78EF 026A [. ] MVO@ R3, R5 ; $78F0 026B [. ] MVO@ R4, R5 ; $78F1 026C [. ] DECR R0 ; $78F2 0010 [. ] BNEQ L78EF ; $78F3 022C 0005 [.. ] PULR R0 ; $78F5 02B0 [. ] ADDI #$003C, R5 ; $78F6 02FD 003C [.< ] SUBR R0, R5 ; $78F8 0105 [. ] SUBR R0, R5 ; $78F9 0105 [. ] SUBR R0, R5 ; $78FA 0105 [. ] DECR R1 ; $78FB 0011 [. ] BNEQ L78EE ; $78FC 022C 000F [.. ] PULR R4 ; $78FE 02B4 [. ] INCR R4 ; $78FF 000C [. ] PULR R7 ; $7900 02B7 [. ] JSR R5, L7918 ; $7901 0004 0178 0118 [...] SDBD ; $7904 0001 [. ] MVI@ R4, R3 ; $7905 02A3 [. ] MVII #$035A, R2 ; $7906 02BA 035A [.. ] MVI@ R2, R2 ; $7908 0292 [. ] B L7912 ; $7909 0200 0007 [.. ] L790B: SLL R0, 2 ; $790B 004C [L ] SLL R0 ; $790C 0048 [H ] XORR R3, R0 ; $790D 01D8 [. ] MVO@ R2, R5 ; $790E 026A [. ] MVO@ R0, R5 ; $790F 0268 [. ] SWAP R0 ; $7910 0040 [@ ] MVO@ R0, R5 ; $7911 0268 [. ] L7912: MVI@ R4, R0 ; $7912 02A0 [. ] SUBI #$0020, R0 ; $7913 0338 0020 [. ] BPL L790B ; $7915 0223 000B [.. ] PULR R7 ; $7917 02B7 [. ] L7918: PSHR R5 ; $7918 0275 [. ] PSHR R0 ; $7919 0270 [. ] PSHR R1 ; $791A 0271 [. ] MVI@ R4, R0 ; $791B 02A0 [. ] MVI@ R4, R1 ; $791C 02A1 [. ] SLL R1, 2 ; $791D 004D [M ] MOVR R1, R5 ; $791E 008D [. ] SLL R1, 2 ; $791F 004D [M ] ADDR R1, R5 ; $7920 00CD [. ] ADDR R0, R5 ; $7921 00C5 [. ] MOVR R5, R0 ; $7922 00A8 [. ] ADDR R0, R5 ; $7923 00C5 [. ] ADDR R0, R5 ; $7924 00C5 [. ] MVII #$035B, R1 ; $7925 02B9 035B [.. ] ADD@ R1, R5 ; $7927 02CD [. ] PULR R1 ; $7928 02B1 [. ] PULR R0 ; $7929 02B0 [. ] PULR R7 ; $792A 02B7 [. ] SUBR R2, R2 ; $792B 0112 [. ] RRC R2 ; $792C 0072 [r ] B L7933 ; $792D 0200 0004 [.. ] MVII #$0080, R2 ; $792F 02BA 0080 [.. ] INCR R7 ; $7931 000F [. ] CLRR R2 ; $7932 01D2 [. ] L7933: JSR R5, L78BC ; $7933 0004 0178 00BC [...] JSR R5, L7918 ; $7936 0004 0178 0118 [...] MVI@ R4, R1 ; $7939 02A1 [. ] SDBD ; $793A 0001 [. ] MVI@ R4, R3 ; $793B 02A3 [. ] PSHR R4 ; $793C 0274 [. ] SDBD ; $793D 0001 [. ] ADDI #$189A, R1 ; $793E 02F9 009A 0018 [...] XORR R3, R2 ; $7941 01DA [. ] B L794F ; $7942 0200 000B [.. ] L7944: TSTR R2 ; $7944 0092 [. ] BMI L794F ; $7945 020B 0008 [.. ] MVII #$035A, R4 ; $7947 02BC 035A [.. ] MVI@ R4, R4 ; $7949 02A4 [. ] MVO@ R4, R5 ; $794A 026C [. ] MVO@ R2, R5 ; $794B 026A [. ] SWAP R2 ; $794C 0042 [B ] MVO@ R2, R5 ; $794D 026A [. ] SWAP R2 ; $794E 0042 [B ] L794F: DECR R1 ; $794F 0011 [. ] MVI@ R1, R4 ; $7950 028C [. ] CMPR R4, R0 ; $7951 0160 [. ] BGE L7957 ; $7952 020D 0003 [.. ] DECR R4 ; $7954 0014 [. ] BNEQ L7944 ; $7955 022C 0012 [.. ] L7957: MVII #$035A, R4 ; $7957 02BC 035A [.. ] MVI@ R4, R4 ; $7959 02A4 [. ] INCR R7 ; $795A 000F [. ] L795B: DECR R1 ; $795B 0011 [. ] MVII #$0078, R2 ; $795C 02BA 0078 [.x ] XORR R3, R2 ; $795E 01DA [. ] L795F: ADDI #$0008, R2 ; $795F 02FA 0008 [.. ] SUB@ R1, R0 ; $7961 0308 [. ] BPL L795F ; $7962 0223 0004 [.. ] ADD@ R1, R0 ; $7964 02C8 [. ] MVO@ R4, R5 ; $7965 026C [. ] MVO@ R2, R5 ; $7966 026A [. ] SWAP R2 ; $7967 0042 [B ] MVO@ R2, R5 ; $7968 026A [. ] MVI@ R1, R2 ; $7969 028A [. ] DECR R2 ; $796A 0012 [. ] BNEQ L795B ; $796B 022C 0011 [.. ] PULR R4 ; $796D 02B4 [. ] PULR R7 ; $796E 02B7 [. ] JSR R5, L789B ; $796F 0004 0178 009B [...] MOVR R1, R0 ; $7972 0088 [. ] MVI@ R4, R1 ; $7973 02A1 [. ] JSR R5, L78C4 ; $7974 0004 0178 00C4 [...] B L7984 ; $7977 0200 000B [.. ] MVII #$0002, R2 ; $7979 02BA 0002 [.. ] INCR R7 ; $797B 000F [. ] CLRR R2 ; $797C 01D2 [. ] DECR R2 ; $797D 0012 [. ] JSR R5, L78BC ; $797E 0004 0178 00BC [...] ADDR R2, R0 ; $7981 00D0 [. ] SUBI #$0002, R5 ; $7982 033D 0002 [.. ] L7984: MVO@ R0, R5 ; $7984 0268 [. ] SWAP R0 ; $7985 0040 [@ ] MVO@ R0, R5 ; $7986 0268 [. ] PULR R7 ; $7987 02B7 [. ] JSR R5, L78BC ; $7988 0004 0178 00BC [...] BNEQ L799C ; $798B 020C 000F [.. ] L798D: MVI@ R4, R0 ; $798D Get a value from @R4 SLL R0, 2 ; $798E \ SLL R0, 2 ; $798F | SLL R0, 2 ; $7990 | NOP ; $7991 |-- Sign extend the DECLE to a full SARC R0, 2 ; $7992 | 16-bit signed value. SARC R0, 2 ; $7993 | SARC R0, 2 ; $7994 / ADDR R0, R4 ; $7995 Add it to R4 to offset pointer PULR R7 ; $7996 Return. JSR R5, L78BC ; $7997 0004 0178 00BC [...] BNEQ L798D ; $799A 022C 000E [.. ] L799C: INCR R4 ; $799C 000C [. ] PULR R7 ; $799D 02B7 [. ] JSR R5, L78BC ; $799E 0004 0178 00BC [...] BPL L798D ; $79A1 0223 0015 [.. ] INCR R4 ; $79A3 000C [. ] PULR R7 ; $79A4 02B7 [. ] JSR R5, L78BC ; $79A5 0004 0178 00BC [...] BMI L798D ; $79A8 022B 001C [.. ] INCR R4 ; $79AA 000C [. ] PULR R7 ; $79AB 02B7 [. ] ADDR R3, R1 ; $79AC 00D9 [. ] INCR R1 ; $79AD 0009 [. ] MVI@ R4, R2 ; $79AE 02A2 [. ] MOVR R2, R3 ; $79AF 0093 [. ] AND@ R1, R2 ; $79B0 038A [. ] CMPR R3, R2 ; $79B1 015A [. ] BEQ L798D ; $79B2 0224 0026 [.& ] INCR R4 ; $79B4 000C [. ] PULR R7 ; $79B5 02B7 [. ] ADDR R3, R1 ; $79B6 00D9 [. ] INCR R1 ; $79B7 0009 [. ] MVI@ R4, R2 ; $79B8 02A2 [. ] AND@ R1, R2 ; $79B9 038A [. ] BEQ L798D ; $79BA 0224 002E [.. ] INCR R4 ; $79BC 000C [. ] PULR R7 ; $79BD 02B7 [. ] ADDR R3, R1 ; $79BE 00D9 [. ] INCR R1 ; $79BF 0009 [. ] MVI@ R4, R2 ; $79C0 02A2 [. ] AND@ R1, R2 ; $79C1 038A [. ] BNEQ L798D ; $79C2 022C 0036 [.6 ] INCR R4 ; $79C4 000C [. ] PULR R7 ; $79C5 02B7 [. ] MOVR R1, R0 ; $79C6 0088 [. ] JSR R5, G1745 ; $79C7 0004 0114 0345 [...] MOVR R0, R1 ; $79CA 0081 [. ] COMR R1 ; $79CB 0019 [. ] INCR R3 ; $79CC 000B [. ] AND@ R3, R1 ; $79CD 0399 [. ] XORR R0, R1 ; $79CE 01C1 [. ] MVO@ R1, R3 ; $79CF 0259 [. ] PULR R7 ; $79D0 02B7 [. ] MOVR R1, R0 ; $79D1 0088 [. ] JSR R5, G1745 ; $79D2 0004 0114 0345 [...] COMR R0 ; $79D5 0018 [. ] INCR R3 ; $79D6 000B [. ] AND@ R3, R0 ; $79D7 0398 [. ] MVO@ R0, R3 ; $79D8 0258 [. ] PULR R7 ; $79D9 02B7 [. ] MVI@ R3, R5 ; $79DA 029D [. ] ADDR R5, R5 ; $79DB 00ED [. ] ADDR R3, R5 ; $79DC 00DD [. ] SUBI #$0050, R5 ; $79DD 033D 0050 [.P ] SDBD ; $79DF 0001 [. ] MVI@ R4, R0 ; $79E0 02A0 [. ] MOVR R4, R1 ; $79E1 00A1 [. ] MVO@ R1, R5 ; $79E2 0269 [. ] SWAP R1 ; $79E3 0041 [A ] MVO@ R1, R5 ; $79E4 0269 [. ] MOVR R0, R4 ; $79E5 0084 [. ] PULR R7 ; $79E6 02B7 [. ] MVI@ R3, R5 ; $79E7 029D [. ] ADDR R5, R5 ; $79E8 00ED [. ] ADDR R3, R5 ; $79E9 00DD [. ] SUBI #$0050, R5 ; $79EA 033D 0050 [.P ] SDBD ; $79EC 0001 [. ] MVI@ R5, R4 ; $79ED 02AC [. ] PULR R7 ; $79EE 02B7 [. ] JSR R5, L7A2C ; $79EF 0004 0178 022C [...] INCR R4 ; $79F2 000C [. ] JSR R5, L7E00 ; $79F3 0004 017C 0200 [...] PSHR R2 ; $79F6 0272 [. ] MOVR R1, R0 ; $79F7 0088 [. ] SAR R0, 2 ; $79F8 006C [l ] SAR R0, 2 ; $79F9 006C [l ] JSR R5, G1DDB ; $79FA 0004 011C 01DB [...] PSHR R2 ; $79FD 0272 [. ] MOVR R3, R0 ; $79FE 0098 [. ] L79FF: SAR R0, 2 ; $79FF 006C [l ] SAR R0, 2 ; $7A00 006C [l ] L7A01: JSR R5, G1DDB ; $7A01 0004 011C 01DB [...] ADD@ R6, R2 ; $7A04 02F2 [. ] L7A05: JSR R5, L7A1C ; $7A05 0004 0178 021C [...] MOVR R2, R1 ; $7A08 0091 [. ] L7A09: SLL R1, 2 ; $7A09 004D [M ] SLL R1, 2 ; $7A0A 004D [M ] PULR R2 ; $7A0B 02B2 [. ] JSR R5, G1DF8 ; $7A0C 0004 011C 01F8 [...] MOVR R0, R2 ; $7A0F 0082 [. ] INCR R4 ; $7A10 000C [. ] B L7A16 ; $7A11 0200 0003 [.. ] JSR R5, L7A2C ; $7A13 0004 0178 022C [...] L7A16: MVO@ R2, R4 ; $7A16 0262 [. ] JSR R5, L7DEA ; $7A17 0004 017C 01EA [...] PULR R4 ; $7A1A 02B4 [. ] PULR R7 ; $7A1B 02B7 [. ] L7A1C: MOVR R2, R1 ; $7A1C 0091 [. ] SWAP R2 ; $7A1D 0042 [B ] ANDI #$00C0, R2 ; $7A1E 03BA 00C0 [.. ] BNEQ L7A25 ; $7A20 020C 0003 [.. ] J G1E23 ; $7A22 0004 031C 0223 [...] L7A25: PSHR R5 ; $7A25 0275 [. ] SLR R1, 2 ; $7A26 0065 [e ] JSR R5, G1E23 ; $7A27 0004 011C 0223 [...] SLL R2 ; $7A2A 004A [J ] PULR R7 ; $7A2B 02B7 [. ] L7A2C: PSHR R5 ; $7A2C 0275 [. ] MOVR R1, R2 ; $7A2D 008A [. ] SDBD ; $7A2E 0001 [. ] MVI@ R4, R5 ; $7A2F 02A5 [. ] INCR R5 ; $7A30 000D [. ] MVI@ R5, R1 ; $7A31 02A9 [. ] MOVR R1, R0 ; $7A32 0088 [. ] JSR R5, G1745 ; $7A33 0004 0114 0345 [...] COMR R0 ; $7A36 0018 [. ] ADDI #$0002, R3 ; $7A37 02FB 0002 [.. ] AND@ R3, R0 ; $7A39 0398 [. ] MVO@ R0, R3 ; $7A3A 0258 [. ] JSR R5, L7DE1 ; $7A3B 0004 017C 01E1 [...] MVI@ R4, R0 ; $7A3E 02A0 [. ] MVI@ R4, R1 ; $7A3F 02A1 [. ] MVI@ R4, R3 ; $7A40 02A3 [. ] INCR R5 ; $7A41 000D [. ] SLL R2 ; $7A42 004A [J ] PSHR R2 ; $7A43 0272 [. ] COMR R2 ; $7A44 001A [. ] AND@ R5, R2 ; $7A45 03AA [. ] XOR@ R6, R2 ; $7A46 03F2 [. ] DECR R5 ; $7A47 0015 [. ] MVO@ R2, R5 ; $7A48 026A [. ] ADDI #$0008, R5 ; $7A49 02FD 0008 [.. ] MVO@ R1, R5 ; $7A4B 0269 [. ] MVO@ R3, R5 ; $7A4C 026B [. ] SUBI #$0003, R5 ; $7A4D 033D 0003 [.. ] PULR R1 ; $7A4F 02B1 [. ] PSHR R4 ; $7A50 0274 [. ] MOVR R5, R4 ; $7A51 00AC [. ] MOVR R0, R2 ; $7A52 0082 [. ] MOVR R1, R7 ; $7A53 008F [. ] SDBD ; $7A54 0001 [. ] MVI@ R4, R5 ; $7A55 02A5 [. ] MVI@ R5, R0 ; $7A56 02A8 [. ] MVI@ R5, R1 ; $7A57 02A9 [. ] JSR R5, L7D57 ; $7A58 0004 017C 0157 [...] SDBD ; $7A5B 0001 [. ] MVI@ R4, R5 ; $7A5C 02A5 [. ] INCR R5 ; $7A5D 000D [. ] MVI@ R5, R1 ; $7A5E 02A9 [. ] JSR R5, L7DE1 ; $7A5F 0004 017C 01E1 [...] CLRR R0 ; $7A62 01C0 [. ] ADDI #$0002, R5 ; $7A63 02FD 0002 [.. ] MVO@ R0, R5 ; $7A65 0268 [. ] ADDI #$0002, R5 ; $7A66 02FD 0002 [.. ] MVO@ R0, R5 ; $7A68 0268 [. ] ADDI #$0003, R5 ; $7A69 02FD 0003 [.. ] MVO@ R0, R5 ; $7A6B 0268 [. ] PULR R7 ; $7A6C 02B7 [. ] JSR R5, L789D ; $7A6D 0004 0178 009D [...] MVI@ R4, R3 ; $7A70 02A3 [. ] MOVR R3, R0 ; $7A71 0098 [. ] BEQ L7A87 ; $7A72 0204 0013 [.. ] MOVR R1, R0 ; $7A74 0088 [. ] MVI@ R4, R1 ; $7A75 02A1 [. ] JSR R5, L7DE1 ; $7A76 0004 017C 01E1 [...] ADDR R3, R5 ; $7A79 00DD [. ] MVO@ R0, R5 ; $7A7A 0268 [. ] PULR R7 ; $7A7B 02B7 [. ] MVII #$000C, R3 ; $7A7C 02BB 000C [.. ] ADDI #$0002, R7 ; $7A7E 02FF 0002 [.. ] MVII #$0004, R3 ; $7A80 02BB 0004 [.. ] JSR R5, L789D ; $7A82 0004 0178 009D [...] MVII #$0111, R0 ; $7A85 02B8 0111 [.. ] L7A87: PSHR R0 ; $7A87 0270 [. ] MOVR R1, R0 ; $7A88 0088 [. ] MVI@ R4, R1 ; $7A89 02A1 [. ] JSR R5, L7DE1 ; $7A8A 0004 017C 01E1 [...] MOVR R5, R2 ; $7A8D 00AA [. ] JSR R5, L7C32 ; $7A8E 0004 017C 0032 [..2] XOR@ R6, R0 ; $7A91 03F0 [. ] ADDR R3, R7 ; $7A92 jump to $7A93, $7A97 or $7A9F MVO@ R0, R2 ; $7A93 0250 [. ] INCR R2 ; $7A94 000A [. ] MVO@ R1, R5 ; $7A95 0269 [. ] PULR R7 ; $7A96 02B7 [. ] COMR R0 ; $7A97 0018 [. ] AND@ R2, R0 ; $7A98 0390 [. ] MVO@ R0, R2 ; $7A99 0250 [. ] INCR R2 ; $7A9A 000A [. ] COMR R1 ; $7A9B 0019 [. ] AND@ R2, R1 ; $7A9C 0391 [. ] MVO@ R1, R2 ; $7A9D 0251 [. ] PULR R7 ; $7A9E 02B7 [. ] MOVR R0, R3 ; $7A9F 0083 [. ] COMR R0 ; $7AA0 0018 [. ] AND@ R2, R0 ; $7AA1 0390 [. ] XORR R3, R0 ; $7AA2 01D8 [. ] MVO@ R0, R2 ; $7AA3 0250 [. ] INCR R2 ; $7AA4 000A [. ] MOVR R1, R3 ; $7AA5 008B [. ] COMR R1 ; $7AA6 0019 [. ] AND@ R2, R1 ; $7AA7 0391 [. ] XORR R3, R1 ; $7AA8 01D9 [. ] MVO@ R1, R2 ; $7AA9 0251 [. ] PULR R7 ; $7AAA 02B7 [. ] SDBD ; $7AAB 0001 [. ] MVI@ R4, R3 ; $7AAC 02A3 [. ] PSHR R4 ; $7AAD 0274 [. ] MOVR R3, R4 ; $7AAE 009C [. ] MOVR R2, R1 ; $7AAF 0091 [. ] SUBI #$003D, R1 ; $7AB0 0339 003D [.= ] MVII #$002D, R0 ; $7AB2 02B8 002D [.- ] JSR R5, G1730 ; $7AB4 0004 0114 0330 [...] B L7AE3 ; $7AB7 0200 002A [.* ] PSHR R4 ; $7AB9 0274 [. ] MOVR R2, R4 ; $7ABA 0094 [. ] SUBI #$003C, R2 ; $7ABB 033A 003C [.< ] CLRR R3 ; $7ABD 01DB [. ] L7ABE: MVI@ R4, R0 ; $7ABE 02A0 [. ] MVII #$035A, R5 ; $7ABF 02BD 035A [.. ] CMP@ R5, R0 ; $7AC1 0368 [. ] BPL L7AD6 ; $7AC2 0203 0012 [.. ] MVI@ R5, R5 ; $7AC4 02AD [. ] SUBI #$003C, R5 ; $7AC5 033D 003C [.< ] B L7ACC ; $7AC7 0200 0003 [.. ] L7AC9: CMP@ R5, R0 ; $7AC9 0368 [. ] BEQ L7AD6 ; $7ACA 0204 000A [.. ] L7ACC: CMPR R5, R2 ; $7ACC 016A [. ] BNEQ L7AC9 ; $7ACD 022C 0005 [.. ] MVO@ R0, R2 ; $7ACF 0250 [. ] INCR R2 ; $7AD0 000A [. ] INCR R3 ; $7AD1 000B [. ] CMPI #$002C, R3 ; $7AD2 037B 002C [., ] BEQ L7AE0 ; $7AD4 0204 000A [.. ] L7AD6: ADDI #$0002, R4 ; $7AD6 02FC 0002 [.. ] MVII #$035B, R5 ; $7AD8 02BD 035B [.. ] MVI@ R5, R0 ; $7ADA 02A8 [. ] ADDI #$02D0, R0 ; $7ADB 02F8 02D0 [.. ] CMPR R0, R4 ; $7ADD 0144 [. ] BNEQ L7ABE ; $7ADE 022C 0021 [.! ] L7AE0: SUBR R3, R2 ; $7AE0 011A [. ] DECR R2 ; $7AE1 0012 [. ] MVO@ R3, R2 ; $7AE2 0253 [. ] L7AE3: JSR R5, L7D06 ; $7AE3 0004 017C 0106 [...] PULR R4 ; $7AE6 02B4 [. ] PULR R7 ; $7AE7 02B7 [. ] SDBD ; $7AE8 0001 [. ] MVI@ R4, R0 ; $7AE9 02A0 [. ] MOVR R2, R5 ; $7AEA 0095 [. ] SUBI #$0047, R5 ; $7AEB 033D 0047 [.G ] B L7984 ; $7AED 0220 016A [.. ] MOVR R2, R1 ; $7AEF 0091 [. ] SUBI #$0045, R1 ; $7AF0 0339 0045 [.E ] MVII #$0008, R0 ; $7AF2 02B8 0008 [.. ] B L78DE ; $7AF4 0220 0217 [.. ] SUBI #$024A, R2 ; $7AF6 033A 024A [.. ] SARC R1, 2 ; $7AF8 007D [} ] BOV L7B06 ; $7AF9 0202 000B [.. ] ADCR R2 ; $7AFB 002A [* ] JSR R5, L78BC ; $7AFC 0004 0178 00BC [...] ANDI #$0007, R0 ; $7AFF 03B8 0007 [.. ] MVO@ R0, R2 ; $7B01 0250 [. ] SUBI #$0002, R5 ; $7B02 033D 0002 [.. ] B L7984 ; $7B04 0220 0181 [.. ] L7B06: ADDI #$0002, R2 ; $7B06 02FA 0002 [.. ] MVO@ R1, R2 ; $7B08 0251 [. ] PULR R7 ; $7B09 02B7 [. ] MOVR R2, R5 ; $7B0A 0095 [. ] SUBI #$000E, R5 ; $7B0B 033D 000E [.. ] MVI@ R5, R0 ; $7B0D 02A8 [. ] INCR R5 ; $7B0E 000D [. ] MVO@ R1, R5 ; $7B0F 0269 [. ] CLRR R1 ; $7B10 01C9 [. ] MVO@ R1, R5 ; $7B11 0269 [. ] PSHR R5 ; $7B12 0275 [. ] JSR R5, L7B23 ; $7B13 0004 0178 0323 [...] PULR R5 ; $7B16 02B5 [. ] SLL R0 ; $7B17 0048 [H ] ADDI #$000A, R0 ; $7B18 02F8 000A [.. ] INCR R7 ; $7B1A 000F [. ] L7B1B: INCR R2 ; $7B1B 000A [. ] SUBI #$0015, R0 ; $7B1C 0338 0015 [.. ] BGE L7B1B ; $7B1E 022D 0004 [.. ] MOVR R2, R0 ; $7B20 0090 [. ] B L7984 ; $7B21 0220 019E [.. ] L7B23: PSHR R5 ; $7B23 0275 [. ] SDBD ; $7B24 0001 [. ] MVII #$8352, R5 ; $7B25 02BD 0052 0083 [.R.] SDBD ; $7B28 0001 [. ] MVI@ R5, R3 ; $7B29 02AB [. ] SDBD ; $7B2A 0001 [. ] ADDI #$8004, R3 ; $7B2B 02FB 0004 0080 [...] L7B2E: MOVR R3, R5 ; $7B2E 009D [. ] SDBD ; $7B2F 0001 [. ] MVI@ R5, R2 ; $7B30 02AA [. ] MOVR R3, R5 ; $7B31 009D [. ] SDBD ; $7B32 0001 [. ] CMP@ R5, R2 ; $7B33 036A [. ] BNEQ L7B2E ; $7B34 022C 0007 [.. ] PULR R7 ; $7B36 02B7 [. ] CLRR R1 ; $7B37 01C9 [. ] MOVR R2, R5 ; $7B38 0095 [. ] SUBI #$0008, R5 ; $7B39 033D 0008 [.. ] MVO@ R1, R5 ; $7B3B 0269 [. ] MVO@ R1, R5 ; $7B3C 0269 [. ] PULR R7 ; $7B3D 02B7 [. ] JSR R5, L789B ; $7B3E 0004 0178 009B [...] MOVR R1, R0 ; $7B41 0088 [. ] MVII #$035B, R5 ; $7B42 02BD 035B [.. ] MVI@ R5, R5 ; $7B44 02AD [. ] SUBI #$0008, R5 ; $7B45 033D 0008 [.. ] SDBD ; $7B47 0001 [. ] SUB@ R5, R0 ; $7B48 0328 [. ] BGT L7832 ; $7B49 022E 0318 [.. ] PULR R7 ; $7B4B 02B7 [. ] SDBD ; $7B4C 0001 [. ] MVI@ R4, R5 ; $7B4D 02A5 [. ] PSHR R4 ; $7B4E 0274 [. ] MOVR R5, R4 ; $7B4F 00AC [. ] MVI@ R4, R0 ; $7B50 02A0 [. ] PSHR R0 ; $7B51 0270 [. ] PSHR R1 ; $7B52 0271 [. ] MVI@ R4, R1 ; $7B53 02A1 [. ] JSR R5, L7DE1 ; $7B54 0004 017C 01E1 [...] PSHR R5 ; $7B57 0275 [. ] JSR R5, L7C31 ; $7B58 0004 017C 0031 [..1] PULR R5 ; $7B5B 02B5 [. ] MVO@ R0, R5 ; $7B5C 0268 [. ] MVO@ R1, R5 ; $7B5D 0269 [. ] PULR R1 ; $7B5E 02B1 [. ] TSTR R1 ; $7B5F 0089 [. ] BEQ L7B70 ; $7B60 0204 000E [.. ] ADDI #$0002, R5 ; $7B62 02FD 0002 [.. ] MVI@ R5, R2 ; $7B64 02AA [. ] ANDI #$00FF, R2 ; $7B65 03BA 00FF [.. ] ADDI #$0002, R5 ; $7B67 02FD 0002 [.. ] MVI@ R5, R3 ; $7B69 02AB [. ] ANDI #$00FF, R3 ; $7B6A 03BB 00FF [.. ] ADDI #$0002, R4 ; $7B6C 02FC 0002 [.. ] B L7B78 ; $7B6E 0200 0008 [.. ] L7B70: MVO@ R1, R5 ; $7B70 0269 [. ] INCR R5 ; $7B71 000D [. ] MVI@ R4, R2 ; $7B72 02A2 [. ] MVO@ R2, R5 ; $7B73 026A [. ] MVO@ R1, R5 ; $7B74 0269 [. ] INCR R5 ; $7B75 000D [. ] MVI@ R4, R3 ; $7B76 02A3 [. ] MVO@ R3, R5 ; $7B77 026B [. ] L7B78: B L7B8C ; $7B78 0200 0012 [.. ] L7B7A: PSHR R0 ; $7B7A 0270 [. ] PSHR R5 ; $7B7B 0275 [. ] JSR R5, L7C31 ; $7B7C 0004 017C 0031 [..1] PULR R5 ; $7B7F 02B5 [. ] XORI #$0080, R0 ; $7B80 03F8 0080 [.. ] MVO@ R0, R5 ; $7B82 0268 [. ] MVO@ R1, R5 ; $7B83 0269 [. ] MVI@ R4, R1 ; $7B84 02A1 [. ] MVO@ R1, R5 ; $7B85 0269 [. ] MVI@ R4, R1 ; $7B86 02A1 [. ] ADDI #$0002, R5 ; $7B87 02FD 0002 [.. ] MVO@ R1, R5 ; $7B89 0269 [. ] ADDI #$0002, R5 ; $7B8A 02FD 0002 [.. ] L7B8C: MVI@ R4, R1 ; $7B8C 02A1 [. ] MVO@ R1, R5 ; $7B8D 0269 [. ] ADDI #$0003, R5 ; $7B8E 02FD 0003 [.. ] PULR R0 ; $7B90 02B0 [. ] DECR R0 ; $7B91 0010 [. ] BNEQ L7B7A ; $7B92 022C 0019 [.. ] PULR R4 ; $7B94 02B4 [. ] PULR R7 ; $7B95 02B7 [. ] SDBD ; $7B96 0001 [. ] MVI@ R4, R5 ; $7B97 02A5 [. ] PSHR R4 ; $7B98 0274 [. ] JSR R4, L7C48 ; $7B99 0004 007C 0048 [.|H] PSHR R1 ; $7B9C 0271 [. ] MVI@ R4, R2 ; $7B9D 02A2 [. ] MVI@ R4, R3 ; $7B9E 02A3 [. ] B L7BAC ; $7B9F 0200 000B [.. ] L7BA1: PSHR R2 ; $7BA1 0272 [. ] L7BA2: JSR R5, L7BF6 ; $7BA2 0004 0178 03F6 [...] INCR R0 ; $7BA5 0008 [. ] DECR R2 ; $7BA6 0012 [. ] BNEQ L7BA2 ; $7BA7 022C 0006 [.. ] PULR R2 ; $7BA9 02B2 [. ] SUBR R2, R0 ; $7BAA 0110 [. ] INCR R1 ; $7BAB 0009 [. ] L7BAC: DECR R3 ; $7BAC 0013 [. ] BPL L7BA1 ; $7BAD 0223 000D [.. ] PULR R3 ; $7BAF 02B3 [. ] MOVR R0, R2 ; $7BB0 0082 [. ] MVI@ R4, R0 ; $7BB1 02A0 [. ] B L7BC9 ; $7BB2 0200 0015 [.. ] L7BB4: PSHR R0 ; $7BB4 0270 [. ] MVI@ R4, R0 ; $7BB5 02A0 [. ] SLL R0, 2 ; $7BB6 004C [L ] SLL R0, 2 ; $7BB7 004C [L ] SLL R0, 2 ; $7BB8 004C [L ] SAR R0, 2 ; $7BB9 006C [l ] MVI@ R4, R1 ; $7BBA 02A1 [. ] SAR R0, 2 ; $7BBB 006C [l ] SAR R0, 2 ; $7BBC 006C [l ] SLL R1, 2 ; $7BBD 004D [M ] SLL R1, 2 ; $7BBE 004D [M ] ADDR R2, R0 ; $7BBF 00D0 [. ] SLL R1, 2 ; $7BC0 004D [M ] SAR R1, 2 ; $7BC1 006D [m ] SAR R1, 2 ; $7BC2 006D [m ] SAR R1, 2 ; $7BC3 006D [m ] ADDR R3, R1 ; $7BC4 00D9 [. ] JSR R5, L7BF6 ; $7BC5 0004 0178 03F6 [...] PULR R0 ; $7BC8 02B0 [. ] L7BC9: DECR R0 ; $7BC9 0010 [. ] BPL L7BB4 ; $7BCA 0223 0017 [.. ] INCR R2 ; $7BCC 000A [. ] SLL R2, 2 ; $7BCD 004E [N ] SLL R2 ; $7BCE 004A [J ] INCR R3 ; $7BCF 000B [. ] SLL R3, 2 ; $7BD0 004F [O ] SLL R3 ; $7BD1 004B [K ] MVI@ R4, R0 ; $7BD2 02A0 [. ] MVI@ R4, R1 ; $7BD3 02A1 [. ] JSR R5, L7DE1 ; $7BD4 0004 017C 01E1 [...] B L7BF1 ; $7BD7 0200 0018 [.. ] L7BD9: PSHR R0 ; $7BD9 0270 [. ] PSHR R5 ; $7BDA 0275 [. ] JSR R5, L7C31 ; $7BDB 0004 017C 0031 [..1] PULR R5 ; $7BDE 02B5 [. ] MVO@ R0, R5 ; $7BDF 0268 [. ] MVO@ R1, R5 ; $7BE0 0269 [. ] CLRR R0 ; $7BE1 01C0 [. ] MVO@ R0, R5 ; $7BE2 0268 [. ] INCR R5 ; $7BE3 000D [. ] MVI@ R4, R1 ; $7BE4 02A1 [. ] ADDR R2, R1 ; $7BE5 00D1 [. ] MVO@ R1, R5 ; $7BE6 0269 [. ] MVO@ R0, R5 ; $7BE7 0268 [. ] INCR R5 ; $7BE8 000D [. ] MVI@ R4, R1 ; $7BE9 02A1 [. ] ADDR R3, R1 ; $7BEA 00D9 [. ] MVO@ R1, R5 ; $7BEB 0269 [. ] MVI@ R4, R1 ; $7BEC 02A1 [. ] MVO@ R1, R5 ; $7BED 0269 [. ] ADDI #$0003, R5 ; $7BEE 02FD 0003 [.. ] PULR R0 ; $7BF0 02B0 [. ] L7BF1: DECR R0 ; $7BF1 0010 [. ] BPL L7BD9 ; $7BF2 0223 001A [.. ] PULR R4 ; $7BF4 02B4 [. ] PULR R7 ; $7BF5 02B7 [. ] L7BF6: PSHR R5 ; $7BF6 0275 [. ] PSHR R1 ; $7BF7 0271 [. ] SLL R1, 2 ; $7BF8 004D [M ] MOVR R1, R5 ; $7BF9 008D [. ] SLL R1, 2 ; $7BFA 004D [M ] ADDR R1, R5 ; $7BFB 00CD [. ] MVI@ R4, R1 ; $7BFC 02A1 [. ] CMPI #$0384, R1 ; $7BFD 0379 0384 [.. ] BGE L7C2F ; $7BFF 020D 002E [.. ] CMPI #$0014, R0 ; $7C01 0378 0014 [.. ] BC L7C2E ; $7C03 0201 0029 [.) ] CMPI #$00F0, R5 ; $7C05 037D 00F0 [.. ] BC L7C2E ; $7C07 0201 0025 [.% ] PSHR R4 ; $7C09 0274 [. ] ADDR R0, R5 ; $7C0A 00C5 [. ] MOVR R5, R4 ; $7C0B 00AC [. ] ADDR R5, R5 ; $7C0C 00ED [. ] ADDR R4, R5 ; $7C0D 00E5 [. ] MVII #$035B, R4 ; $7C0E 02BC 035B [.. ] ADD@ R4, R5 ; $7C10 02E5 [. ] PULR R4 ; $7C11 02B4 [. ] SARC R1 ; $7C12 0079 [y ] BNC L7C1F ; $7C13 0209 000A [.. ] PSHR R1 ; $7C15 0271 [. ] MVII #$035A, R1 ; $7C16 02B9 035A [.. ] MVI@ R1, R1 ; $7C18 0289 [. ] MVO@ R1, R5 ; $7C19 0269 [. ] MVI@ R4, R1 ; $7C1A 02A1 [. ] SWAP R1 ; $7C1B 0041 [A ] ADD@ R6, R1 ; $7C1C 02F1 [. ] B L7C29 ; $7C1D 0200 000A [.. ] L7C1F: MVO@ R1, R5 ; $7C1F 0269 [. ] MVI@ R4, R1 ; $7C20 02A1 [. ] ANDI #$0007, R1 ; $7C21 03B9 0007 [.. ] PSHR R1 ; $7C23 0271 [. ] DECR R4 ; $7C24 0014 [. ] XOR@ R4, R1 ; $7C25 03E1 [. ] SLL R1, 2 ; $7C26 004D [M ] SLL R1, 2 ; $7C27 004D [M ] XOR@ R6, R1 ; $7C28 03F1 [. ] L7C29: MVO@ R1, R5 ; $7C29 0269 [. ] SWAP R1 ; $7C2A 0041 [A ] MVO@ R1, R5 ; $7C2B 0269 [. ] PULR R1 ; $7C2C 02B1 [. ] PULR R7 ; $7C2D 02B7 [. ] L7C2E: INCR R4 ; $7C2E 000C [. ] L7C2F: PULR R1 ; $7C2F 02B1 [. ] PULR R7 ; $7C30 02B7 [. ] ;; The following function slices up "W" as follows: ;; ;; 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ;; +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ;; R0: | - | - | - | - | - | - |W_9| 1 | - |W_6|W_5| 1 |W_3|W_2|W_1| 1 | ;; +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ;; ;; 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ;; +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ;; R1: | - | - | - | - | - | - |W_8|W_7| - |W_4|W_0| - | - | - | - | - | ;; +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ ;; L7C31: MVI@ R4, R0 ; $7C31 Get a word from @R0 L7C32: PSHR R5 ; $7C32 Save return addr MOVR R0, R1 ; $7C33 Copy word ANDI #$026E, R0 ; $7C34 Keep bits 1,2,3,5,6,9 XORI #$0111, R0 ; $7C36 Set bits 0,4,8 SLL R1 ; $7C38 R1 = word << 1 MOVR R1, R5 ; $7C39 R5 = word << 1 ANDI #$0300, R5 ; $7C3A R5 = (word << 1) & 0x300 PSHR R5 ; $7C3C Save R5 SLL R1 ; $7C3D R1 = word << 2 MOVR R1, R5 ; $7C3E copy to R5 ANDI #$0040, R5 ; $7C3F R5 = (word << 2) & 0x040 SLL R1, 2 ; $7C41 \_ R1 = word << 5 SLL R1 ; $7C42 / ANDI #$0020, R1 ; $7C43 R1 = (word << 5) & 0x020 XORR R5, R1 ; $7C45 \_ R1 = ((w<<5)&0x020) ^ XOR@ R6, R1 ; $7C46 / ((w<<2)&0x040) ^ PULR R7 ; $7C47 ((w<<1)&0x300); L7C48: PSHR R4 ; $7C48 0274 [. ] MVI@ R5, R0 ; $7C49 02A8 [. ] MVI@ R5, R1 ; $7C4A 02A9 [. ] SDBD ; $7C4B 0001 [. ] MVI@ R5, R4 ; $7C4C 02AC [. ] ADD@ R4, R0 ; $7C4D 02E0 [. ] SLL R0, 2 ; $7C4E 004C [L ] SLL R0, 2 ; $7C4F 004C [L ] SLL R0, 2 ; $7C50 004C [L ] SAR R0, 2 ; $7C51 006C [l ] ADD@ R4, R1 ; $7C52 02E1 [. ] SAR R0, 2 ; $7C53 006C [l ] SAR R0, 2 ; $7C54 006C [l ] SLL R1, 2 ; $7C55 004D [M ] SLL R1, 2 ; $7C56 004D [M ] NOP ; $7C57 0034 [4 ] SLL R1, 2 ; $7C58 004D [M ] SAR R1, 2 ; $7C59 006D [m ] SAR R1, 2 ; $7C5A 006D [m ] SAR R1, 2 ; $7C5B 006D [m ] PULR R7 ; $7C5C 02B7 [. ] SDBD ; $7C5D 0001 [. ] MVI@ R4, R5 ; $7C5E 02A5 [. ] PSHR R4 ; $7C5F 0274 [. ] JSR R4, L7C48 ; $7C60 0004 007C 0048 [.|H] PSHR R1 ; $7C63 0271 [. ] MVI@ R4, R2 ; $7C64 02A2 [. ] MVI@ R4, R3 ; $7C65 02A3 [. ] B L7C73 ; $7C66 0200 000B [.. ] L7C68: PSHR R2 ; $7C68 0272 [. ] L7C69: JSR R5, L7CA0 ; $7C69 0004 017C 00A0 [...] INCR R0 ; $7C6C 0008 [. ] DECR R2 ; $7C6D 0012 [. ] BNEQ L7C69 ; $7C6E 022C 0006 [.. ] PULR R2 ; $7C70 02B2 [. ] SUBR R2, R0 ; $7C71 0110 [. ] INCR R1 ; $7C72 0009 [. ] L7C73: DECR R3 ; $7C73 0013 [. ] BPL L7C68 ; $7C74 0223 000D [.. ] PULR R3 ; $7C76 02B3 [. ] MOVR R0, R2 ; $7C77 0082 [. ] MVI@ R4, R0 ; $7C78 02A0 [. ] INCR R6 ; $7C79 000E [. ] B L7C93 ; $7C7A 0200 0017 [.. ] L7C7C: PSHR R0 ; $7C7C 0270 [. ] MVI@ R4, R0 ; $7C7D 02A0 [. ] SLL R0, 2 ; $7C7E 004C [L ] SLL R0, 2 ; $7C7F 004C [L ] SLL R0, 2 ; $7C80 004C [L ] NOP ; $7C81 0034 [4 ] SARC R0, 2 ; $7C82 007C [| ] SARC R0, 2 ; $7C83 007C [| ] SARC R0, 2 ; $7C84 007C [| ] ADDR R2, R0 ; $7C85 00D0 [. ] MVI@ R4, R1 ; $7C86 02A1 [. ] SLL R1, 2 ; $7C87 004D [M ] SLL R1, 2 ; $7C88 004D [M ] SLL R1, 2 ; $7C89 004D [M ] NOP ; $7C8A 0034 [4 ] SARC R1, 2 ; $7C8B 007D [} ] SARC R1, 2 ; $7C8C 007D [} ] SARC R1, 2 ; $7C8D 007D [} ] ADDR R3, R1 ; $7C8E 00D9 [. ] JSR R5, L7CA0 ; $7C8F 0004 017C 00A0 [...] PULR R0 ; $7C92 02B0 [. ] L7C93: DECR R0 ; $7C93 0010 [. ] BPL L7C7C ; $7C94 0223 0019 [.. ] DECR R6 ; $7C96 0016 [. ] MVI@ R4, R0 ; $7C97 02A0 [. ] MVI@ R4, R1 ; $7C98 02A1 [. ] JSR R5, L7D56 ; $7C99 0004 017C 0156 [...] PULR R4 ; $7C9C 02B4 [. ] ADDI #$0003, R4 ; $7C9D 02FC 0003 [.. ] PULR R7 ; $7C9F 02B7 [. ] L7CA0: PSHR R5 ; $7CA0 0275 [. ] PSHR R1 ; $7CA1 0271 [. ] SLL R1, 2 ; $7CA2 004D [M ] MOVR R1, R5 ; $7CA3 008D [. ] SLL R1, 2 ; $7CA4 004D [M ] ADDR R1, R5 ; $7CA5 00CD [. ] MVI@ R4, R1 ; $7CA6 02A1 [. ] CMPI #$0384, R1 ; $7CA7 0379 0384 [.. ] BGE L7CC7 ; $7CA9 020D 001C [.. ] CMPI #$0014, R0 ; $7CAB 0378 0014 [.. ] BC L7CC6 ; $7CAD 0201 0017 [.. ] CMPI #$00F0, R5 ; $7CAF 037D 00F0 [.. ] BC L7CC6 ; $7CB1 0201 0013 [.. ] PSHR R4 ; $7CB3 0274 [. ] ADDR R0, R5 ; $7CB4 00C5 [. ] MOVR R5, R4 ; $7CB5 00AC [. ] ADDR R5, R5 ; $7CB6 00ED [. ] ADDR R4, R5 ; $7CB7 00E5 [. ] MVII #$035B, R4 ; $7CB8 02BC 035B [.. ] ADD@ R4, R5 ; $7CBA 02E5 [. ] MOVR R6, R4 ; $7CBB 00B4 [. ] SUBI #$0006, R4 ; $7CBC 033C 0006 [.. ] MVI@ R4, R4 ; $7CBE 02A4 [. ] MVI@ R4, R1 ; $7CBF 02A1 [. ] MVO@ R1, R5 ; $7CC0 0269 [. ] MVI@ R4, R1 ; $7CC1 02A1 [. ] MVO@ R1, R5 ; $7CC2 0269 [. ] MVI@ R4, R1 ; $7CC3 02A1 [. ] MVO@ R1, R5 ; $7CC4 0269 [. ] PULR R4 ; $7CC5 02B4 [. ] L7CC6: INCR R4 ; $7CC6 000C [. ] L7CC7: PULR R1 ; $7CC7 02B1 [. ] PULR R7 ; $7CC8 02B7 [. ] L7CC9: PSHR R5 ; $7CC9 0275 [. ] MOVR R7, R0 ; $7CCA 00B8 [. ] ADDI #$000D, R0 ; $7CCB 02F8 000D [.. ] MVII #$0100, R4 ; $7CCD 02BC 0100 [.. ] MOVR R4, R5 ; $7CCF 00A5 [. ] DIS ; $7CD0 0003 [. ] SDBD ; $7CD1 0001 [. ] MVI@ R4, R1 ; $7CD2 02A1 [. ] MVO@ R0, R5 ; $7CD3 0268 [. ] SWAP R0 ; $7CD4 0040 [@ ] MVO@ R0, R5 ; $7CD5 0268 [. ] EIS ; $7CD6 0002 [. ] DECR R7 ; $7CD7 0017 [. ] SUBI #$0008, R6 ; $7CD8 033E 0008 [.. ] MVII #$0100, R4 ; $7CDA 02BC 0100 [.. ] MVO@ R1, R4 ; $7CDC 0261 [. ] SWAP R1 ; $7CDD 0041 [A ] MVO@ R1, R4 ; $7CDE 0261 [. ] PULR R7 ; $7CDF 02B7 [. ] L7CE0: PSHR R5 ; $7CE0 0275 [. ] JSR R5, L7CC9 ; $7CE1 0004 017C 00C9 [...] MVII #$0021, R5 ; $7CE4 02BD 0021 [.! ] MVO@ R0, R5 ; $7CE6 0268 [. ] MVII #$035B, R5 ; $7CE7 02BD 035B [.. ] MVI@ R5, R5 ; $7CE9 02AD [. ] SUBI #$024B, R5 ; $7CEA 033D 024B [.. ] MVI@ R5, R0 ; $7CEC 02A8 [. ] MVII #$002C, R5 ; $7CED 02BD 002C [., ] MVO@ R0, R5 ; $7CEF 0268 [. ] MOVR R0, R1 ; $7CF0 0081 [. ] ANDI #$000B, R1 ; $7CF1 03B9 000B [.. ] XORR R1, R0 ; $7CF3 01C8 [. ] SWAP R1 ; $7CF4 0041 [A ] SWAP R0 ; $7CF5 0040 [@ ] SLL R0, 2 ; $7CF6 004C [L ] XORR R0, R1 ; $7CF7 01C1 [. ] SLL R1 ; $7CF8 0049 [I ] MVII #$0200, R4 ; $7CF9 02BC 0200 [.. ] MVII #$00F0, R0 ; $7CFB 02B8 00F0 [.. ] JSR R5, G1741 ; $7CFD 0004 0114 0341 [...] MVII #$0008, R0 ; $7D00 02B8 0008 [.. ] CLRR R4 ; $7D02 01E4 [. ] JSR R5, G1739 ; $7D03 0004 0114 0339 [...] L7D06: PSHR R5 ; $7D06 0275 [. ] MVII #$035B, R3 ; $7D07 02BB 035B [.. ] MVI@ R3, R3 ; $7D09 029B [. ] SUBI #$000E, R3 ; $7D0A 033B 000E [.. ] MOVR R3, R5 ; $7D0C 009D [. ] CLRR R0 ; $7D0D 01C0 [. ] MVO@ R0, R3 ; $7D0E 0258 [. ] SUBI #$002F, R3 ; $7D0F 033B 002F [./ ] MVI@ R3, R0 ; $7D11 0298 [. ] MOVR R0, R1 ; $7D12 0081 [. ] MVII #$002C, R2 ; $7D13 02BA 002C [., ] SUBR R0, R2 ; $7D15 0102 [. ] SLR R2 ; $7D16 0062 [b ] BNEQ L7D1F ; $7D17 020C 0006 [.. ] MVII #$0014, R2 ; $7D19 02BA 0014 [.. ] MVII #$002C, R0 ; $7D1B 02B8 002C [., ] MVII #$0018, R1 ; $7D1D 02B9 0018 [.. ] L7D1F: ADDR R2, R1 ; $7D1F 00D1 [. ] ADDI #$0009, R5 ; $7D20 02FD 0009 [.. ] MVO@ R2, R5 ; $7D22 026A [. ] MOVR R0, R2 ; $7D23 0082 [. ] SLL R1, 2 ; $7D24 004D [M ] SLL R1 ; $7D25 0049 [I ] MVO@ R1, R5 ; $7D26 0269 [. ] SLL R0, 2 ; $7D27 004C [L ] SLL R0 ; $7D28 0048 [H ] MVO@ R0, R5 ; $7D29 0268 [. ] BEQ L7D55 ; $7D2A 0204 0029 [.) ] JSR R5, L7CE0 ; $7D2C 0004 017C 00E0 [...] DIS ; $7D2F 0003 [. ] MVII #$035B, R5 ; $7D30 02BD 035B [.. ] MVI@ R5, R5 ; $7D32 02AD [. ] SUBI #$0047, R5 ; $7D33 033D 0047 [.G ] SDBD ; $7D35 0001 [. ] MVI@ R5, R1 ; $7D36 02A9 [. ] SDBD ; $7D37 0001 [. ] MVII #$3800, R5 ; $7D38 02BD 0000 0038 [..8] L7D3B: INCR R3 ; $7D3B 000B [. ] MVI@ R3, R4 ; $7D3C 029C [. ] ADDR R4, R4 ; $7D3D 00E4 [. ] ADDR R4, R4 ; $7D3E 00E4 [. ] ADDR R4, R4 ; $7D3F 00E4 [. ] ADDR R1, R4 ; $7D40 00CC [. ] MVI@ R4, R0 ; $7D41 02A0 [. ] MVO@ R0, R5 ; $7D42 0268 [. ] MVI@ R4, R0 ; $7D43 02A0 [. ] MVO@ R0, R5 ; $7D44 0268 [. ] MVI@ R4, R0 ; $7D45 02A0 [. ] MVO@ R0, R5 ; $7D46 0268 [. ] MVI@ R4, R0 ; $7D47 02A0 [. ] MVO@ R0, R5 ; $7D48 0268 [. ] MVI@ R4, R0 ; $7D49 02A0 [. ] MVO@ R0, R5 ; $7D4A 0268 [. ] MVI@ R4, R0 ; $7D4B 02A0 [. ] MVO@ R0, R5 ; $7D4C 0268 [. ] MVI@ R4, R0 ; $7D4D 02A0 [. ] MVO@ R0, R5 ; $7D4E 0268 [. ] MVI@ R4, R0 ; $7D4F 02A0 [. ] MVO@ R0, R5 ; $7D50 0268 [. ] DECR R2 ; $7D51 0012 [. ] BNEQ L7D3B ; $7D52 022C 0018 [.. ] EIS ; $7D54 0002 [. ] L7D55: PULR R7 ; $7D55 02B7 [. ] L7D56: PSHR R5 ; $7D56 0275 [. ] L7D57: JSR R5, L7DE1 ; $7D57 0004 017C 01E1 [...] B L7D63 ; $7D5A 0200 0007 [.. ] L7D5C: MVI@ R5, R1 ; $7D5C 02A9 [. ] DECR R5 ; $7D5D 0015 [. ] ANDI #$03FE, R1 ; $7D5E 03B9 03FE [.. ] MVO@ R1, R5 ; $7D60 0269 [. ] ADDI #$000B, R5 ; $7D61 02FD 000B [.. ] L7D63: DECR R0 ; $7D63 0010 [. ] BPL L7D5C ; $7D64 0223 0009 [.. ] PULR R7 ; $7D66 02B7 [. ] PSHR R5 ; $7D67 0275 [. ] MVII #$035B, R3 ; $7D68 02BB 035B [.. ] MVI@ R3, R3 ; $7D6A 029B [. ] SUBI #$0045, R3 ; $7D6B 033B 0045 [.E ] MVII #$035C, R4 ; $7D6D 02BC 035C [.. ] MVI@ R4, R4 ; $7D6F 02A4 [. ] MOVR R4, R5 ; $7D70 00A5 [. ] ADDI #$0060, R5 ; $7D71 02FD 0060 [.` ] MVII #$0008, R0 ; $7D73 02B8 0008 [.. ] L7D75: PSHR R0 ; $7D75 0270 [. ] MVI@ R4, R0 ; $7D76 02A0 [. ] SARC R0 ; $7D77 0078 [x ] BNC L7DD9 ; $7D78 0209 005F [._ ] MVI@ R4, R2 ; $7D7A 02A2 [. ] MOVR R0, R1 ; $7D7B 0081 [. ] ANDI #$0180, R1 ; $7D7C 03B9 0180 [.. ] SLL R1, 2 ; $7D7E 004D [M ] ADDI #$0002, R4 ; $7D7F 02FC 0002 [.. ] XOR@ R4, R1 ; $7D81 03E1 [. ] MVO@ R1, R5 ; $7D82 0269 [. ] SWAP R1 ; $7D83 0041 [A ] MVO@ R1, R5 ; $7D84 0269 [. ] ADDI #$000E, R5 ; $7D85 02FD 000E [.. ] ANDI #$03E0, R2 ; $7D87 03BA 03E0 [.. ] SLL R2, 2 ; $7D89 004E [N ] ADDI #$0002, R4 ; $7D8A 02FC 0002 [.. ] MVI@ R4, R1 ; $7D8C 02A1 [. ] CMPI #$0080, R1 ; $7D8D 0379 0080 [.. ] BNC L7D93 ; $7D8F 0209 0002 [.. ] MVII #$0070, R1 ; $7D91 02B9 0070 [.p ] L7D93: XORR R1, R2 ; $7D93 01CA [. ] MVO@ R2, R5 ; $7D94 026A [. ] SWAP R2 ; $7D95 0042 [B ] MVO@ R2, R5 ; $7D96 026A [. ] ADDI #$000E, R5 ; $7D97 02FD 000E [.. ] MOVR R0, R1 ; $7D99 0081 [. ] ANDI #$0038, R1 ; $7D9A 03B9 0038 [.8 ] SWAP R1 ; $7D9C 0041 [A ] ANDI #$0007, R0 ; $7D9D 03B8 0007 [.. ] XORR R0, R1 ; $7D9F 01C1 [. ] CLRR R0 ; $7DA0 01C0 [. ] RLC R2 ; $7DA1 0052 [R ] BNC L7DA5 ; $7DA2 0209 0001 [.. ] INCR R0 ; $7DA4 0008 [. ] L7DA5: MVI@ R3, R2 ; $7DA5 029A [. ] INCR R3 ; $7DA6 000B [. ] XORR R2, R1 ; $7DA7 01D1 [. ] MVO@ R1, R5 ; $7DA8 0269 [. ] SWAP R1 ; $7DA9 0041 [A ] MVO@ R1, R5 ; $7DAA 0269 [. ] PSHR R5 ; $7DAB 0275 [. ] MVI@ R4, R5 ; $7DAC 02A5 [. ] ADDR R5, R5 ; $7DAD 00ED [. ] ADDR R5, R5 ; $7DAE 00ED [. ] ADDR R5, R5 ; $7DAF 00ED [. ] PSHR R4 ; $7DB0 0274 [. ] MVII #$035B, R4 ; $7DB1 02BC 035B [.. ] MVI@ R4, R4 ; $7DB3 02A4 [. ] SUBI #$0047, R4 ; $7DB4 033C 0047 [.G ] SDBD ; $7DB6 0001 [. ] ADD@ R4, R5 ; $7DB7 02E5 [. ] SUBI #$0202, R4 ; $7DB8 033C 0202 [.. ] ADDR R2, R4 ; $7DBA 00D4 [. ] L7DBB: MVI@ R5, R1 ; $7DBB 02A9 [. ] MVO@ R1, R4 ; $7DBC 0261 [. ] MVI@ R5, R1 ; $7DBD 02A9 [. ] MVO@ R1, R4 ; $7DBE 0261 [. ] MVI@ R5, R1 ; $7DBF 02A9 [. ] MVO@ R1, R4 ; $7DC0 0261 [. ] MVI@ R5, R1 ; $7DC1 02A9 [. ] MVO@ R1, R4 ; $7DC2 0261 [. ] MVI@ R5, R1 ; $7DC3 02A9 [. ] MVO@ R1, R4 ; $7DC4 0261 [. ] MVI@ R5, R1 ; $7DC5 02A9 [. ] MVO@ R1, R4 ; $7DC6 0261 [. ] MVI@ R5, R1 ; $7DC7 02A9 [. ] MVO@ R1, R4 ; $7DC8 0261 [. ] MVI@ R5, R1 ; $7DC9 02A9 [. ] MVO@ R1, R4 ; $7DCA 0261 [. ] DECR R0 ; $7DCB 0010 [. ] BPL L7DBB ; $7DCC 0223 0012 [.. ] PULR R4 ; $7DCE 02B4 [. ] PULR R5 ; $7DCF 02B5 [. ] ADDI #$0003, R4 ; $7DD0 02FC 0003 [.. ] SUBI #$0020, R5 ; $7DD2 033D 0020 [. ] L7DD4: PULR R0 ; $7DD4 02B0 [. ] DECR R0 ; $7DD5 0010 [. ] BNEQ L7D75 ; $7DD6 022C 0062 [.b ] PULR R7 ; $7DD8 02B7 [. ] L7DD9: CLRR R0 ; $7DD9 01C0 [. ] MVO@ R0, R5 ; $7DDA 0268 [. ] MVO@ R0, R5 ; $7DDB 0268 [. ] INCR R3 ; $7DDC 000B [. ] ADDI #$000B, R4 ; $7DDD 02FC 000B [.. ] B L7DD4 ; $7DDF 0220 000C [.. ] L7DE1: PSHR R5 ; $7DE1 SLL R1, 2 ; $7DE2 \_ R5 = R1 * 4 MOVR R1, R5 ; $7DE3 / SLL R1 ; $7DE4 \_ R5 = R1 * 12 ADDR R1, R5 ; $7DE5 / MVII #$035C, R1 ; $7DE6 \_ R5 = R1 * 12 + PEEK($035C) ADD@ R1, R5 ; $7DE8 / PULR R7 ; $7DE9 L7DEA: PSHR R5 ; $7DEA 0275 [. ] PSHR R4 ; $7DEB 0274 [. ] JSR R5, L7E00 ; $7DEC 0004 017C 0200 [...] MOVR R2, R4 ; $7DEF 0094 [. ] JSR R5, G1DF8 ; $7DF0 0004 011C 01F8 [...] MOVR R3, R1 ; $7DF3 0099 [. ] MOVR R4, R2 ; $7DF4 00A2 [. ] PULR R4 ; $7DF5 02B4 [. ] SUBI #$0008, R4 ; $7DF6 033C 0008 [.. ] MVO@ R0, R4 ; $7DF8 0260 [. ] JSR R5, G1DF8 ; $7DF9 0004 011C 01F8 [...] ADDI #$0002, R4 ; $7DFC 02FC 0002 [.. ] MVO@ R0, R4 ; $7DFE 0260 [. ] PULR R7 ; $7DFF 02B7 [. ] L7E00: PSHR R5 ; $7E00 0275 [. ] MVI@ R4, R1 ; $7E01 02A1 [. ] MVI@ R4, R3 ; $7E02 02A3 [. ] SUBI #$0008, R4 ; $7E03 033C 0008 [.. ] MVI@ R4, R0 ; $7E05 02A0 [. ] ANDI #$00FF, R0 ; $7E06 03B8 00FF [.. ] CMPI #$00D0, R0 ; $7E08 0378 00D0 [.. ] BNC L7E0E ; $7E0A 0209 0002 [.. ] XORI #$0300, R0 ; $7E0C 03F8 0300 [.. ] L7E0E: SUBR R0, R1 ; $7E0E 0101 [. ] SLL R1, 2 ; $7E0F 004D [M ] SLL R1, 2 ; $7E10 004D [M ] SLL R1, 2 ; $7E11 004D [M ] SAR R1, 2 ; $7E12 006D [m ] ADDI #$0002, R4 ; $7E13 02FC 0002 [.. ] MVI@ R4, R0 ; $7E15 02A0 [. ] JSR R5, G1668 ; $7E16 0004 0114 0268 [...] SUBR R0, R3 ; $7E19 0103 [. ] SLL R3, 2 ; $7E1A 004F [O ] SLL R3, 2 ; $7E1B 004F [O ] SLL R3, 2 ; $7E1C 004F [O ] SAR R3, 2 ; $7E1D 006F [o ] PULR R7 ; $7E1E 02B7 [. ] PSHR R5 ; $7E1F 0275 [. ] MVII #$0110, R4 ; $7E20 02BC 0110 [.. ] MVO@ R2, R4 ; $7E22 0262 [. ] SWAP R2 ; $7E23 0042 [B ] MVO@ R2, R4 ; $7E24 0262 [. ] MOVR R1, R5 ; $7E25 008D [. ] MVO@ R1, R4 ; $7E26 0261 [. ] SWAP R1 ; $7E27 0041 [A ] MVO@ R1, R4 ; $7E28 0261 [. ] CLRR R0 ; $7E29 01C0 [. ] MVO@ R0, R4 ; $7E2A 0260 [. ] MVI@ R3, R0 ; $7E2B 0298 [. ] INCR R3 ; $7E2C 000B [. ] MOVR R7, R1 ; $7E2D 00B9 [. ] DECR R1 ; $7E2E 0011 [. ] PSHR R1 ; $7E2F 0271 [. ] MVI@ R3, R1 ; $7E30 0299 [. ] INCR R3 ; $7E31 000B [. ] SARC R1 ; $7E32 0079 [y ] CLRR R2 ; $7E33 01D2 [. ] BNC L7E38 ; $7E34 0209 0002 [.. ] MVI@ R3, R2 ; $7E36 029A [. ] INCR R3 ; $7E37 000B [. ] L7E38: PSHR R0 ; $7E38 0270 [. ] PSHR R5 ; $7E39 0275 [. ] PSHR R3 ; $7E3A 0273 [. ] MVII #$0108, R4 ; $7E3B 02BC 0108 [.. ] SARC R2 ; $7E3D 007A [z ] BNC L7E42 ; $7E3E 0209 0002 [.. ] B L7ED4 ; $7E40 0200 0092 [.. ] L7E42: SARC R2 ; $7E42 007A [z ] BC L7E74 ; $7E43 0201 002F [./ ] SARC R2 ; $7E45 007A [z ] BC L7EBF ; $7E46 0201 0077 [.w ] JSR R5, L7F94 ; $7E48 0004 017C 0394 [...] MVII #$0110, R5 ; $7E4B 02BD 0110 [.. ] SDBD ; $7E4D 0001 [. ] MVI@ R5, R4 ; $7E4E 02AC [. ] SARC R2 ; $7E4F 007A [z ] BNC L7E54 ; $7E50 0209 0002 [.. ] SDBD ; $7E52 0001 [. ] MVI@ R5, R4 ; $7E53 02AC [. ] L7E54: SWAP R1 ; $7E54 0041 [A ] SLL R1, 2 ; $7E55 004D [M ] SARC R2, 2 ; $7E56 007E [~ ] RRC R1, 2 ; $7E57 0075 [u ] SWAP R1 ; $7E58 0041 [A ] MVII #$0114, R5 ; $7E59 02BD 0114 [.. ] MVI@ R5, R0 ; $7E5B 02A8 [. ] DECR R5 ; $7E5C 0015 [. ] ADDR R0, R1 ; $7E5D 00C1 [. ] SUBR R0, R2 ; $7E5E 0102 [. ] BEQ L7E67 ; $7E5F 0204 0006 [.. ] PULR R2 ; $7E61 02B2 [. ] SUBI #$0002, R2 ; $7E62 033A 0002 [.. ] PSHR R2 ; $7E64 0272 [. ] MOVR R0, R2 ; $7E65 0082 [. ] INCR R2 ; $7E66 000A [. ] L7E67: MVO@ R2, R5 ; $7E67 026A [. ] SLL R1, 2 ; $7E68 004D [M ] ADDR R1, R1 ; $7E69 00C9 [. ] ADDR R1, R4 ; $7E6A 00CC [. ] MVII #$0108, R1 ; $7E6B 02B9 0108 [.. ] MVII #$0008, R0 ; $7E6D 02B8 0008 [.. ] JSR R5, G1730 ; $7E6F 0004 0114 0330 [...] B L7F08 ; $7E72 0200 0094 [.. ] L7E74: MOVR R1, R0 ; $7E74 0088 [. ] ANDI #$0080, R0 ; $7E75 03B8 0080 [.. ] XORR R0, R1 ; $7E77 01C1 [. ] SARC R2 ; $7E78 007A [z ] RLC R0 ; $7E79 0050 [P ] CLRR R3 ; $7E7A 01DB [. ] SARC R2, 2 ; $7E7B 007E [~ ] RLC R3, 2 ; $7E7C 0057 [W ] SARC R2 ; $7E7D 007A [z ] RLC R3 ; $7E7E 0053 [S ] SARC R0 ; $7E7F 0078 [x ] RLC R2 ; $7E80 0052 [R ] SLL R0, 2 ; $7E81 004C [L ] SWAP R0 ; $7E82 0040 [@ ] TSTR R3 ; $7E83 009B [. ] BNEQ L7E89 ; $7E84 020C 0003 [.. ] MOVR R0, R3 ; $7E86 0083 [. ] SLL R3, 2 ; $7E87 004F [O ] CLRR R0 ; $7E88 01C0 [. ] L7E89: PSHR R0 ; $7E89 0270 [. ] PSHR R3 ; $7E8A 0273 [. ] JSR R5, L7F84 ; $7E8B 0004 017C 0384 [...] PULR R5 ; $7E8E 02B5 [. ] MVII #$0200, R0 ; $7E8F 02B8 0200 [.. ] L7E91: SLR R0 ; $7E91 0060 [` ] DECR R5 ; $7E92 0015 [. ] BPL L7E91 ; $7E93 0223 0003 [.. ] SWAP R2 ; $7E95 0042 [B ] SLL R1, 2 ; $7E96 004D [M ] XORR R2, R1 ; $7E97 01D1 [. ] XOR@ R6, R1 ; $7E98 03F1 [. ] SLL R1, 2 ; $7E99 004D [M ] SLL R1, 2 ; $7E9A 004D [M ] L7E9B: JSR R5, L7F9D ; $7E9B 0004 017C 039D [...] SLLC R1 ; $7E9E 0059 [Y ] BNC L7E9B ; $7E9F 0229 0005 [.. ] SLLC R1 ; $7EA1 0059 [Y ] BNC L7EB1 ; $7EA2 0209 000D [.. ] L7EA4: SLR R0 ; $7EA4 0060 [` ] BNEQ L7EA9 ; $7EA5 020C 0002 [.. ] MVII #$0100, R0 ; $7EA7 02B8 0100 [.. ] L7EA9: JSR R5, L7F9D ; $7EA9 0004 017C 039D [...] SLLC R1 ; $7EAC 0059 [Y ] BNC L7EA4 ; $7EAD 0229 000A [.. ] B L7E9B ; $7EAF 0220 0015 [.. ] L7EB1: SLL R0 ; $7EB1 0048 [H ] ANDI #$01FF, R0 ; $7EB2 03B8 01FF [.. ] BNEQ L7EB7 ; $7EB4 020C 0001 [.. ] INCR R0 ; $7EB6 0008 [. ] L7EB7: JSR R5, L7F9D ; $7EB7 0004 017C 039D [...] SLLC R1 ; $7EBA 0059 [Y ] BNC L7EB1 ; $7EBB 0229 000B [.. ] B L7E9B ; $7EBD 0220 0023 [.# ] L7EBF: CLRR R3 ; $7EBF 01DB [. ] SWAP R2 ; $7EC0 0042 [B ] SLL R2 ; $7EC1 004A [J ] XORR R2, R1 ; $7EC2 01D1 [. ] L7EC3: MVII #$0004, R0 ; $7EC3 02B8 0004 [.. ] L7EC5: RLC R1 ; $7EC5 0051 [Q ] RRC R2 ; $7EC6 0072 [r ] SAR R2 ; $7EC7 006A [j ] DECR R0 ; $7EC8 0010 [. ] BNEQ L7EC5 ; $7EC9 022C 0005 [.. ] SWAP R2 ; $7ECB 0042 [B ] MVO@ R2, R4 ; $7ECC 0262 [. ] MVO@ R2, R4 ; $7ECD 0262 [. ] CMPI #$0110, R4 ; $7ECE 037C 0110 [.. ] BNEQ L7EC3 ; $7ED0 022C 000E [.. ] B L7F08 ; $7ED2 0200 0034 [.4 ] L7ED4: JSR R5, L7F84 ; $7ED4 0004 017C 0384 [...] MOVR R3, R0 ; $7ED7 0098 [. ] ANDI #$0004, R0 ; $7ED8 03B8 0004 [.. ] ADDR R0, R0 ; $7EDA 00C0 [. ] XORR R0, R3 ; $7EDB 01C3 [. ] SWAP R2 ; $7EDC 0042 [B ] SLL R1, 2 ; $7EDD 004D [M ] XORR R2, R1 ; $7EDE 01D1 [. ] CLRR R0 ; $7EDF 01C0 [. ] DECR R4 ; $7EE0 0014 [. ] L7EE1: SLR R0 ; $7EE1 0060 [` ] BNEQ L7EE6 ; $7EE2 020C 0002 [.. ] MVII #$0100, R0 ; $7EE4 02B8 0100 [.. ] L7EE6: JSR R5, L7F9D ; $7EE6 0004 017C 039D [...] SLLC R1 ; $7EE9 0059 [Y ] BNC L7EE1 ; $7EEA 0229 000A [.. ] SLLC R1 ; $7EEC 0059 [Y ] BNC L7EF7 ; $7EED 0209 0008 [.. ] L7EEF: JSR R5, L7F9D ; $7EEF 0004 017C 039D [...] SLLC R1 ; $7EF2 0059 [Y ] BNC L7EEF ; $7EF3 0229 0005 [.. ] B L7EE1 ; $7EF5 0220 0015 [.. ] L7EF7: DECR R4 ; $7EF7 0014 [. ] SLR R0 ; $7EF8 0060 [` ] BNEQ L7F00 ; $7EF9 020C 0005 [.. ] TSTR R1 ; $7EFB 0089 [. ] BEQ L7F08 ; $7EFC 0204 000A [.. ] MVII #$0100, R0 ; $7EFE 02B8 0100 [.. ] L7F00: JSR R5, L7F9D ; $7F00 0004 017C 039D [...] SLLC R1 ; $7F03 0059 [Y ] BNC L7EF7 ; $7F04 0229 000E [.. ] B L7EE1 ; $7F06 0220 0026 [.& ] L7F08: SLL R3, 2 ; $7F08 004F [O ] SWAP R3 ; $7F09 0043 [C ] SLLC R3, 2 ; $7F0A 005F [_ ] BNOV L7F27 ; $7F0B 020A 001A [.. ] MVII #$0108, R4 ; $7F0D 02BC 0108 [.. ] MOVR R4, R5 ; $7F0F 00A5 [. ] L7F10: MVI@ R4, R1 ; $7F10 02A1 [. ] ANDI #$00FF, R1 ; $7F11 03B9 00FF [.. ] BEQ L7F22 ; $7F13 0204 000D [.. ] MVII #$0008, R0 ; $7F15 02B8 0008 [.. ] L7F17: DECR R0 ; $7F17 0010 [. ] RRC R1 ; $7F18 0071 [q ] BNC L7F17 ; $7F19 0229 0003 [.. ] RRC R1 ; $7F1B 0071 [q ] INCR R7 ; $7F1C 000F [. ] L7F1D: SAR R1 ; $7F1D 0069 [i ] DECR R0 ; $7F1E 0010 [. ] BPL L7F1D ; $7F1F 0223 0003 [.. ] SWAP R1 ; $7F21 0041 [A ] L7F22: MVO@ R1, R5 ; $7F22 0269 [. ] CMPI #$0110, R5 ; $7F23 037D 0110 [.. ] BNEQ L7F10 ; $7F25 022C 0016 [.. ] L7F27: SLLC R3 ; $7F27 005B [[ ] BNC L7F3A ; $7F28 0209 0010 [.. ] MVII #$0108, R4 ; $7F2A 02BC 0108 [.. ] MOVR R4, R5 ; $7F2C 00A5 [. ] L7F2D: MVI@ R4, R1 ; $7F2D 02A1 [. ] MVII #$0004, R0 ; $7F2E 02B8 0004 [.. ] L7F30: SARC R1, 2 ; $7F30 007D [} ] RLC R2, 2 ; $7F31 0056 [V ] DECR R0 ; $7F32 0010 [. ] BNEQ L7F30 ; $7F33 022C 0004 [.. ] MVO@ R2, R5 ; $7F35 026A [. ] CMPI #$0110, R5 ; $7F36 037D 0110 [.. ] BNEQ L7F2D ; $7F38 022C 000C [.. ] L7F3A: SLLC R3 ; $7F3A 005B [[ ] BNC L7F4A ; $7F3B 0209 000D [.. ] MVII #$0108, R4 ; $7F3D 02BC 0108 [.. ] MOVR R4, R5 ; $7F3F 00A5 [. ] MVII #$010F, R2 ; $7F40 02BA 010F [.. ] L7F42: MVI@ R4, R0 ; $7F42 02A0 [. ] MVI@ R2, R1 ; $7F43 0291 [. ] MVO@ R1, R5 ; $7F44 0269 [. ] MVO@ R0, R2 ; $7F45 0250 [. ] DECR R2 ; $7F46 0012 [. ] CMPR R4, R2 ; $7F47 0162 [. ] BGT L7F42 ; $7F48 022E 0007 [.. ] L7F4A: SLLC R3 ; $7F4A 005B [[ ] BNC L7F57 ; $7F4B 0209 000A [.. ] MVII #$0108, R4 ; $7F4D 02BC 0108 [.. ] MOVR R4, R5 ; $7F4F 00A5 [. ] L7F50: MVI@ R4, R1 ; $7F50 02A1 [. ] COMR R1 ; $7F51 0019 [. ] MVO@ R1, R5 ; $7F52 0269 [. ] CMPI #$0110, R5 ; $7F53 037D 0110 [.. ] BNEQ L7F50 ; $7F55 022C 0006 [.. ] L7F57: SLLC R3 ; $7F57 005B [[ ] BNC L7F74 ; $7F58 0209 001A [.. ] MVII #$0008, R0 ; $7F5A 02B8 0008 [.. ] L7F5C: MVII #$0108, R4 ; $7F5C 02BC 0108 [.. ] MOVR R4, R5 ; $7F5E 00A5 [. ] L7F5F: MVI@ R4, R1 ; $7F5F 02A1 [. ] SARC R1 ; $7F60 0079 [y ] RRC R2 ; $7F61 0072 [r ] MVO@ R1, R5 ; $7F62 0269 [. ] CMPI #$0110, R5 ; $7F63 037D 0110 [.. ] BNEQ L7F5F ; $7F65 022C 0007 [.. ] SWAP R2 ; $7F67 0042 [B ] PSHR R2 ; $7F68 0272 [. ] DECR R0 ; $7F69 0010 [. ] BNEQ L7F5C ; $7F6A 022C 000F [.. ] MVII #$0108, R4 ; $7F6C 02BC 0108 [.. ] L7F6E: PULR R1 ; $7F6E 02B1 [. ] MVO@ R1, R4 ; $7F6F 0261 [. ] CMPI #$0110, R4 ; $7F70 037C 0110 [.. ] BNEQ L7F6E ; $7F72 022C 0005 [.. ] L7F74: PULR R3 ; $7F74 02B3 [. ] MVII #$0108, R4 ; $7F75 02BC 0108 [.. ] PULR R5 ; $7F77 02B5 [. ] L7F78: MVI@ R4, R0 ; $7F78 02A0 [. ] MVO@ R0, R5 ; $7F79 0268 [. ] CMPI #$0110, R4 ; $7F7A 037C 0110 [.. ] BNEQ L7F78 ; $7F7C 022C 0005 [.. ] PULR R0 ; $7F7E 02B0 [. ] DECR R0 ; $7F7F 0010 [. ] BNEQ L7F83 ; $7F80 020C 0001 [.. ] PULR R5 ; $7F82 02B5 [. ] L7F83: PULR R7 ; $7F83 02B7 [. ] L7F84: CLRR R0 ; $7F84 01C0 [. ] L7F85: MVO@ R0, R4 ; $7F85 0260 [. ] CMPI #$0110, R4 ; $7F86 037C 0110 [.. ] BNEQ L7F85 ; $7F88 022C 0004 [.. ] SUBI #$0008, R4 ; $7F8A 033C 0008 [.. ] MOVR R1, R3 ; $7F8C 008B [. ] ANDI #$0100, R3 ; $7F8D 03BB 0100 [.. ] BEQ L7F94 ; $7F8F 0204 0003 [.. ] XORR R3, R1 ; $7F91 01D9 [. ] SLL R3 ; $7F92 004B [K ] XORR R3, R1 ; $7F93 01D9 [. ] L7F94: MOVR R1, R3 ; $7F94 008B [. ] ANDI #$03C0, R3 ; $7F95 03BB 03C0 [.. ] XORR R3, R1 ; $7F97 01D9 [. ] SLL R3, 2 ; $7F98 004F [O ] SWAP R3 ; $7F99 0043 [C ] SARC R2 ; $7F9A 007A [z ] RLC R3 ; $7F9B 0053 [S ] MOVR R5, R7 ; $7F9C 00AF [. ] L7F9D: CMPI #$0110, R4 ; $7F9D 037C 0110 [.. ] BEQ L7F08 ; $7F9F 0224 0098 [.. ] PSHR R5 ; $7FA1 0275 [. ] MOVR R0, R5 ; $7FA2 0085 [. ] XOR@ R4, R5 ; $7FA3 03E5 [. ] DECR R4 ; $7FA4 0014 [. ] MVO@ R5, R4 ; $7FA5 0265 [. ] PULR R7 ; $7FA6 02B7 [. ] PSHR R5 ; $7FA7 0275 [. ] PSHR R2 ; $7FA8 0272 [. ] CLRR R1 ; $7FA9 01C9 [. ] CLRR R2 ; $7FAA 01D2 [. ] L7FAB: JSR R5, L7FC9 ; $7FAB 0004 017C 03C9 [...] ANDI #$0002, R5 ; $7FAE 03BD 0002 [.. ] SETC ; $7FB0 0007 [. ] BNEQ L7FC4 ; $7FB1 020C 0011 [.. ] JSR R5, L7FDB ; $7FB3 0004 017C 03DB [...] GSWD R0 ; $7FB6 0030 [0 ] RSWD R1 ; $7FB7 0039 [9 ] BNC L7FC4 ; $7FB8 0209 000A [.. ] INCR R2 ; $7FBA 000A [. ] SUBI #$0030, R0 ; $7FBB 0338 0030 [.0 ] SLL R1 ; $7FBD 0049 [I ] PSHR R1 ; $7FBE 0271 [. ] SLL R1, 2 ; $7FBF 004D [M ] ADD@ R6, R1 ; $7FC0 02F1 [. ] ADDR R0, R1 ; $7FC1 00C1 [. ] B L7FAB ; $7FC2 0220 0018 [.. ] L7FC4: MOVR R0, R5 ; $7FC4 0085 [. ] MOVR R1, R0 ; $7FC5 0088 [. ] MOVR R2, R1 ; $7FC6 0091 [. ] PULR R2 ; $7FC7 02B2 [. ] PULR R7 ; $7FC8 02B7 [. ] L7FC9: PSHR R5 ; $7FC9 0275 [. ] L7FCA: JSR R5, L752E ; $7FCA 0004 0174 012E [...] CMPI #$000D, R0 ; $7FCD 0378 000D [.. ] BNEQ L7FDA ; $7FCF 020C 0009 [.. ] SDBD ; $7FD1 0001 [. ] MVII #$8340, R5 ; $7FD2 02BD 0040 0083 [.@.] MVI@ R5, R5 ; $7FD5 02AD [. ] ANDI #$0010, R5 ; $7FD6 03BD 0010 [.. ] BNEQ L7FCA ; $7FD8 022C 000F [.. ] L7FDA: PULR R7 ; $7FDA 02B7 [. ] L7FDB: CMP@ R5, R0 ; $7FDB 0368 [. ] BLT L7FE3 ; $7FDC 0205 0005 [.. ] CMP@ R5, R0 ; $7FDE 0368 [. ] BGT L7FE4 ; $7FDF 020E 0003 [.. ] SETC ; $7FE1 0007 [. ] MOVR R5, R7 ; $7FE2 00AF [. ] L7FE3: INCR R5 ; $7FE3 000D [. ] L7FE4: CLRC ; $7FE4 0006 [. ] MOVR R5, R7 ; $7FE5 00AF [. ] MOVR R0, R1 ; $7FE6 0081 [. ] L7FE7: PSHR R5 ; $7FE7 0275 [. ] PSHR R2 ; $7FE8 0272 [. ] MVII #$000A, R2 ; $7FE9 02BA 000A [.. ] JSR R5, G1DFB ; $7FEB 0004 011C 01FB [...] PULR R2 ; $7FEE 02B2 [. ] PSHR R1 ; $7FEF 0271 [. ] MOVR R0, R1 ; $7FF0 0081 [. ] BEQ L7FF6 ; $7FF1 0204 0003 [.. ] JSR R5, L7FE7 ; $7FF3 0004 017C 03E7 [...] L7FF6: PULR R0 ; $7FF6 02B0 [. ] ADDI #$0030, R0 ; $7FF7 02F8 0030 [.0 ] JSR R5, L73DD ; $7FF9 0004 0170 03DD [...] HLT ; $7FFC 0000 [. ] HLT ; $7FFD 0000 [. ] HLT ; $7FFE 0000 [. ] SUB@ R6, R2 ; $7FFF 0332 [. ]