Instruction Reference Table


,---------------------.
|Register To Register |
+---------------------+------------------------------------------------------+
|Mnemonics          Operation            Microcycles      Comments           |
+---------+--------------------------------+-----+---------------------------+
| MOVR    | MOVe Register                  | 6/7 |                           |
+---------+--------------------------------+-----+---------------------------+
| TSTR    | TeST Register                  | 6/7 |  MOVR to itself           |
+---------+--------------------------------+-----+---------------------------+
| JR      | Jump to address in Register    |  7  |  MOVR to PC               |
+---------+--------------------------------+-----+---------------------------+
| ADDR    | ADD contents of Registers      | 6/7 |                           |
+---------+--------------------------------+-----+---------------------------+
| SUBR    | SUBtract contents of Registers | 6/7 |                           |
+---------+--------------------------------+-----+---------------------------+
| CMPR    | CoMPare Registers by subtr.    | 6/7 |  Results not stored       |
+---------+--------------------------------+-----+---------------------------+
| ANDR    | logical AND Registers          | 6/7 |                           |
+---------+--------------------------------+-----+---------------------------+
| XORR    | eXclusive OR Registers         | 6/7 |                           |
+---------+--------------------------------+-----+---------------------------+
| CLRR    | CLeaR Register                 | 6/7 |  XORR with itself         |
`----------------------------------------------------------------------------'

*7 cycles if destination register is R6 or R7, 6 cycles otherwise.

                                                                   
,---------------------.
|Single Register      |
+---------------------+------------------------------------------------------.
|Mnemonics          Operation           Microcycles      Comments            |
+---------+-------------------------------+-----+----------------------------+
| INCR    | INCrement Register            | 6/7 |                            |
+---------+-------------------------------+-----+----------------------------+
| DECR    | DECrement Register            | 6/7 |                            |
+---------+-------------------------------+-----+----------------------------+
| COMR    | COMplement Register           | 6/7 |  One's Complement          |
+---------+-------------------------------+-----+----------------------------+
| NEGR    | NEGate Register               | 6/7 |  Two's Complement          |
+---------+-------------------------------+-----+----------------------------+
| ADCR    | ADd Carry Bit to Register     | 6/7 |                            |
+---------+-------------------------------+-----+----------------------------+
| GSWD    | Get Status WorD               | 6/7 |                            |
+---------+-------------------------------+-----+----------------------------+
| NOP     | No OPeration                  | 6/7 |                            |
+---------+-------------------------------+-----+----------------------------+
| SIN     | Software INterrupt            | 6/7 |  Pulse to PCIT pin         |
+---------+-------------------------------+-----+----------------------------+
| RSWD    | Return Status WorD            | 6/7 |                            |
`---------+-------------------------------+-----+----------------------------'

                                                   
,---------------------.
|Register Shift       |
+---------------------+------------------------------------------------------.
|Mnemonics          Operation          Microcycles      Comments             |
+---------+-------------------------------+----+-----------------------------+
| SWAP    | SWAP 8-bit bytes              | 6  |  ---.                       |
+---------+-------------------------------+----+     |                       |
| SLL     | Shift Logical Left            | 6  |     |                       |
+---------+-------------------------------+----+     |   Not interruptable.  |
| RLC     | Rotate Left thru Carry        | 6  |     |                       |
+---------+-------------------------------+----+     |  One or two position  |
| SLLC    | Shift Logical Left thru Carry | 6  |     |   shift capability.   |
+---------+-------------------------------+----+     +--                     |
| SLR     | Shift Logical Right           | 6  |     |   Two position SWAP   |
+---------+-------------------------------+----+     |   replicates lower    |
| SAR     | Shift Arithmetic Right        | 6  |     |  byte in both halves. |
+---------+-------------------------------+----+     |                       |
| RRC     | Rotate Right thru Carry       | 6  |     |   (Add two cycles for |
+---------+-------------------------------+----+     |    2-position shift)  |
| SARC    | Shift Arithmetic Right thru   | 6  |  ---'                       |
|         | Carry                         |    |                             |
`---------+-------------------------------+----+-----------------------------'

                                                             
,---------------------.
|Control Instructions |
+---------------------+------------------------------------------------------.
|Mnemonics          Operation          Microcycles      Comments             |
+---------+-------------------------------+----+-----------------------------+
| HLT     | HaLT                          | 4  | Halts machine completely    |
+---------+-------------------------------+----+-----------------------------+
| SDBD    | Set Double Byte Data          | 4  | Must precede external       |
+---------+-------------------------------+----+-reference to double byte----+
| EIS     | Enable Interrupt System       | 4  |  --.    data                |
+---------+-------------------------------+----+    |                        |
| DIS     | Disable Interrupt System      | 4  |    |                        |
+---------+-------------------------------+----+    |                        |
| TCI     | Terminate Current Interrupt   | 4  |    +-  Not interruptable    |
+---------+-------------------------------+- --+    |                        |
| CLRC    | CLeaR Carry to zero           | 4  |    |                        |
+---------+-------------------------------+----+    |                        |
| SETC    | SET Carry to one              | 4  |  --'                        |
`---------+-------------------------------+----+-----------------------------'


,---------------------.
|Jump Instructions    |
+---------------------+------------------------------------------------------.
|Mnemonics          Operation          Microcycles      Comments             |
+---------+-------------------------------+----+-----------------------------+
| J       | Jump                          | 12 |                             |
+---------+-------------------------------+----+-----------------------------+
| JE      | Jump, Enable, interrupt       | 12 |                             |
+---------+-------------------------------+----+-----------------------------+
| JD      | Jump, Disable interrupt       | 12 |                             |
+---------+-------------------------------+----+-----------------------------+
| JSR     | Jump, Save Return             | 12 |  --.                        |
+---------+-------------------------------+----+    |                        |
| JSRE    | Jump, Save Return & Enable    | 12 |    +--  Return Address      |
+---------+-------------------------------+----+    |     saved in R4,       |
| JSRD    | Jump, Save Return & Disable   | 12 |    |       5 or 6           |
|         | interrupt                     |    |  --'                        |
`---------+-------------------------------+----+-----------------------------'



EXTERNAL REFERENCE INSTRUCTIONS
                                       Note:
,---------------------------------.    Add 2 cycles if test condition is
|Conditional Branch Instructions  |    true except "*"
+----------------------------------+-----------------------------------------.
|Mnemonics           Operation            Microcycles     Comments           |
+---------+---------------------------------+-----+--------------------------+
| B       |  unconditional Branch           |  9* |                          |
+---------+---------------------------------+-----+--------------------------+
| NOPP    |  NO OPeration                   |  7* |   Two words              |
+---------+---------------------------------+-----+--------------------------+
| BC      |  Branch on Carry                |  7  |   C = 1                  |
+---------+---------------------------------+-----+--------------------------+
| BNC     |  Branch on No Carry             |  7  |   C = 0                  |
+---------+---------------------------------+-----+--------------------------+
| BOV     |  Branch on OVerflow             |  7  |   OV = 1                 |
+---------+---------------------------------+-----+--------------------------+
| BNOV    |  Branch on No OVerflow          |  7  |   OV = 0                 |
+---------+---------------------------------+-----+--------------------------+
| BPL     |  Branch on PLus                 |  7  |   S = 0                  |
+---------+---------------------------------+-----+--------------------------+
| BMI     |  Branch on Minus                |  7  |   S = 1                  |
+---------+---------------------------------+-----+--------------------------+
| BEQ     | Branch if Not Zero or Not EQual |  7  |   Z = 1                  |
+---------+---------------------------------+-----+--------------------------+
| BNEQ    | Branch if Not Zero or Not EQual |  7  |   Z = 0                  |
+---------+---------------------------------+-----+--------------------------+
| BLT     |  Branch if Less Than            |  7  |   S XOR OV = 1           |
+---------+---------------------------------+-----+--------------------------+
| BGE     | Branch if Greater than or Equal |  7  |   S XOR OV = 0           |
+---------+---------------------------------+-----+--------------------------+
| BLE     |  Branch if Less than or Equal   |  7  |   Z OR (S XOR OV) = 1    |
+---------+---------------------------------+-----+--------------------------+
| BGT     |  Branch if Greater Than         |  7  |   Z OR (S XOR OV) = 0    |
+---------+---------------------------------+-----+--------------------------+
| BUSC    |  Branch if Sign not = Carry     |  7  |   C XOR S = 1            |
+---------+---------------------------------+-----+--------------------------+
| BESC    |  Branch if Sign = Carry         |  7  |   C XOR S = 0            |
+---------+---------------------------------+-----+--------------------------+
|         | Branch if External condition is |     |  LSB of instruction are  |
| BEXT    |               True              |  7  |  decoded select 1 of 16  |
|         |                                 |     |  external conditions     |
`---------+---------------------------------+-----+--------------------------'


                                                                               
,---------------------.
|  Input/Output       |
+---------------------+------------------------------------------------------.
|Mnemonics     Operation               Microcycles            Comments       |
+---------------------------------+----+----+------+-----+-------------------+
|                                 |Dir.|Imm.|Indir.|Stack|                   |
+---------+-----------------------+----+----+------+-----+-------------------+
| MVO     | MoVe Out              | 11 |  9 |  9   |  9  | Not interruptable |
+---------+-----------------------+----+----+------+-----+-------------------+
| PSHR    | PuSH Register to Stack|  - | -  |  -   |  9  | PSHR = MVO@R6     |
|         |                       |    |    |      |     | Not interruptable |
+---------+-----------------------+----+----+------+-----+-------------------+
| MVI     | MoVe in               | 10 |  8 |  8   | 11  |                   |
+---------+-----------------------+----+----+------+-----+-------------------+
| PULR    | PULl from stack to    |  - |  - |  -   | 11  | PULR = MVI@R6     |
|         |     Register          |    |    |      |     |                   |
`---------+-----------------------+----+----+------+-----+-------------------' 


,---------------------.
|  Arithmetic & Logic |
+---------------------+------------------------------------------------------.
|Mnemonics     Operation               Microcycles            Comments       |
+---------------------------------+----+----+------+-----+-------------------+
|                                 |Dir.|Imm.|Indir.|Stack|                   |
+---------+-----------------------+----+----+------+-----+-------------------+
| ADD     | ADD                   | 10 |  8 |  8   | 11  |                   |
+---------+-----------------------+----+----+------+-----+-------------------+
| SUB     | SUBtract              | 10 |  8 |  8   | 11  |                   |
+---------+-----------------------+----+----+------+-----+-------------------+
| CMP     | CoMPare               | 10 |  8 |  8   | 11  | Result not saved  |
+---------+-----------------------+----+----+------+-----+-------------------+
| AND     | logical AND           | 10 |  8 |  8   | 11  |                   |
+---------+-----------------------+----+----+------+-----+-------------------+
| XOR     | eXclusive OR          | 10 |  8 |  8   | 11  |                   |
`---------+-----------------------+----+----+------+-----+-------------------'